Search results for "FP"
showing 10 items of 297 documents
A Dual-Core Coprocessor with Native 4D Clifford Algebra Support
2012
Geometric or Clifford Algebra (CA) is a powerful mathematical tool that is attracting a growing attention in many research fields such as computer graphics, computer vision, robotics and medical imaging for its natural and intuitive way to represent geometric objects and their transformations. This paper introduces the architecture of CliffordCoreDuo, an embedded dual-core coprocessor that offers direct hardware support to four-dimensional (4D) Clifford algebra operations. A prototype implementation on an FPGA board is detailed. Experimental results show a 1.6× average speedup of CliffordCoreDuo in comparison with the baseline mono-core architecture. A potential cycle speedup of about 40× o…
Fixed-size Quadruples for a New, Hardware-Oriented Representation of the 4D Clifford Algebra
2010
Clifford algebra (geometric algebra) offers a natural and intuitive way to model geometry in fields as robotics, machine vision and computer graphics. This paper proposes a new representation based on fixed-size elements (quadruples) of 4D Clifford algebra and demonstrates that this choice leads to an algorithmic simplification which in turn leads to a simpler and more compact hardware implementation of the algebraic operations. In order to prove the advantages of the new, quadruple-based representation over the classical representation based on homogeneous elements, a coprocessing core supporting the new fixed-size Clifford operands, namely Quad-CliffoSor (Quadruple-based Clifford coproces…
Design Space Exploration of Parallel Embedded Architectures for Native Clifford Algebra Operations
2012
In the past few decades, Geometric or Clifford algebra (CA) has received a growing attention in many research fields, such as robotics, machine vision and computer graphics, as a natural and intuitive way to model geometric objects and their transformations. At the same time, the high dimensionality of Clifford algebra and its computational complexity demand specialized hardware architectures for the direct support of Clifford data types and operators. This paper presents the design space exploration of parallel embedded architectures for native execution of four-dimensional (4D) and five-dimensional (5D) Clifford algebra operations. The design space exploration has been described along wit…
An FPGA Implementation of a Quadruple-Based Multiplier for 4D Clifford Algebra
2008
Geometric or Clifford algebra is an interesting paradigm for geometric modeling in fields as computer graphics, machine vision and robotics. In these areas the research effort is actually aimed at finding an efficient implementation of geometric algebra. The best way to exploit the symbolic computing power of geometric algebra is to support its data types and operators directly in hardware. However the natural representation of the algebra elements as variable-length objects causes some problems in the case of a hardware implementation. This paper proposes a 4D Clifford algebra in which the variable-length elements are mapped into fixed-length elements (quadruples). This choice leads to a s…
Embedded Coprocessors for Native Execution of Geometric Algebra Operations
2016
Clifford algebra or geometric algebra (GA) is a simple and intuitive way to model geometric objects and their transformations. Operating in high-dimensional vector spaces with significant computational costs, the practical use of GA requires dedicated software and/or hardware architectures to directly support Clifford data types and operators. In this paper, a family of embedded coprocessors for the native execution of GA operations is presented. The paper shows the evolution of the coprocessor family focusing on the latest two architectures that offer direct hardware support to up to five-dimensional Clifford operations. The proposed coprocessors exploit hardware-oriented representations o…
A Programmable Networked Processing Node for 3D Brain Vessels Reconstruction
2011
Real-time 3D imaging represents a developing trend in medical imaging. However, most of the 3D medical imaging algorithms are computationally intensive. In this paper, a programmable networked node for 3D brain vessels reconstruction is proposed. Starting from 2D PC-MRA (Phase-Contrast Magnetic Resonance Angiography) sequences, the node is able to generate the 3D brain vasculature using the MIP (Maximum Intensity Projection) algorithm. The node has been prototyped on the Celoxica RC203E board, equipped with a Virtex II FPGA, to get the advantages of an hardware implementation, reaching a better throughput with respect to analogous software implementations. Its generality and programmable ca…
La Sicilia nel FP7: attori, progetti e reti
2013
I finanziamenti europei al sistema della Ricerca, Sviluppo e Innovazione (RSI) rappresentano un contributo fondamentale alla crescita della competitività delle economie regionali. Le risorse comunitarie si vanno ad integrare con quelle statali e regionali a sostegno delle imprese, contribuendo all’attivazione di numerose iniziative di ricerca da parte di chi nell’ambito di un partenariato unisce le proprie competenze e strutture produttive attorno ad un’idea progettuale più o meno prossima al mercato. Questo studio prende in esame la partecipazione del sistema della ricerca e produttivo siciliano (in primis imprese, università, istituti di ricerca) al principale programma europeo per la RSI…
Design and Validation of a FPGA-Based HIL Simulator for Minimum Losses Control of a PMSM
2021
This work examines the FPGA programmable logic platforms applied to minimum losses control of a Permanent Magnet Synchronous Motor (PMSM), which represents a flexible solution for the implementation of an advanced digital control algorithm, given their intrinsic parallel structure and the capability to be directly reprogrammable in the field. In particular, design and validation of a FPGA-based Hardware-In-the-Loop (HIL) simulator is proposed, by investigating about data format, quantization and discretization effects and other issues arising during the experimental validation of a controller prototype, in order to reduce the embedded software development cycle and test control systems. The…
Système de vision à haute gamme dynamique auto adaptable
2020
High dynamic range (HDR) image generation using temporal exposure bracketing is widely used to recover the whole dynamic range of a filmed scene by fusion of two or more low dynamic range (LDR) images. Temporal exposure bracketing technique should be employed for static scenes and it cannot be applied directly for dynamic scenes. Motions introduced by moving objects in the LDR stack images create ghosts artifacts in the reconstructed HDR image. In this thesis, we have studied and evaluated a large nuber of algorithms used to correct or avoid these artifacts and we mad a trade-off between robustness and complexity in order to propose a real-time HDR video generation system.The real-time HDR …
A Software Defined Radio Platform Implementing a WiFi and ZigBee Receiver
2006
A successful attempt to design and implement a multi-standard compliant Basebnd Processor is here presented. By exploiting the potential of FPGA's reconfigurability, the received signal from RF stage have been processed in order to properly decode frames of IEEE 802.11 (WiFi) and IEEE 802.15.4 (ZigBee) protocols. both falling within the ISM band (centered at 2.45GHz). The experimental implementation carried out is a practical demonstration of the Software Defined Radio concept.