0000000000141444

AUTHOR

Steve Furber

showing 4 related works from this author

Live demonstration: multiplexing AER asynchronous channels over LVDS Links with Flow-Control and Clock-Correction for Scalable Neuromorphic Systems

2017

Paper presented at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), held in Baltimore, MD, USA, on 28-31 May 2017.

Computer scienceSerial communicationGabor filters02 engineering and technologyMultiplexingMultiplexing0202 electrical engineering electronic engineering information engineeringComputerSystemsOrganization_SPECIAL-PURPOSEANDAPPLICATION-BASEDSYSTEMSField-programmable gate arrayComputer Science::Operating SystemsMassively parallelNeuromorphicsReal-time systemsSpiking neural networkQuantitative Biology::Neurons and CognitionArtificial neural networkbusiness.industry020208 electrical & electronic engineeringField programmable gate arraysNeuromorphic engineeringAsynchronous communicationEmbedded systemVoltage controlbusinessComputer hardwareNeural networksHardware_LOGICDESIGN
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Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems

2017

Paper presented at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), held in Baltimore, MD, USA, on 28-31 May 2017.

Flow control (data)Neuromorphic Systembusiness.industryComputer scienceVirtual Wiring020208 electrical & electronic engineeringScalable Neuromorphic SystemsScalable Neuromoriphic02 engineering and technologyAddress event representation (AER)Multiplexing020202 computer hardware & architectureHandshakingNeuromorphic engineeringTransmission (telecommunications)Asynchronous communicationEmbedded system0202 electrical engineering electronic engineering information engineeringbusinessField-programmable gate arrayAER (Address Event Representation)Computer hardwareNeuromorphic SystemsHardware_LOGICDESIGN
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On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs f…

2017

Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation …

Computer sciencebusiness.industry020208 electrical & electronic engineeringBiomedical EngineeringSignal Processing Computer-AssistedEquipment Design02 engineering and technologyDifferential signalingHandshakingTransmission (telecommunications)Neuromorphic engineeringAsynchronous communicationEmbedded systemVHDL0202 electrical engineering electronic engineering information engineeringVerilog020201 artificial intelligence & image processingNeural Networks ComputerElectrical and Electronic EngineeringField-programmable gate arraybusinesscomputercomputer.programming_language
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26th Annual Computational Neuroscience Meeting (CNS*2017): Part 2

2017

International audience; No abstract available

0301 basic medicineCerebellumComputer science[SDV]Life Sciences [q-bio]General Neurosciencelcsh:QP351-495Meeting Abstractslcsh:RC321-57103 medical and health sciencesCellular and Molecular Neurosciencelcsh:Neurophysiology and neuropsychology030104 developmental biologymedicine.anatomical_structuremedicineNeuronlcsh:Neurosciences. Biological psychiatry. NeuropsychiatryNeuroscienceComputingMilieux_MISCELLANEOUScomputational neuroscienceBMC Neuroscience
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