0000000000193718
AUTHOR
El-bay Bourennane
showing 9 related works from this author
SECURE PROTOCOL FOR MODERN SCADA
2013
International audience
NoC based virtualized FPGA as cloud Services
2016
International audience; Web-based applications are increasingly demanding many computationally intensive services. On the other hand, FPGA-based hardware accelerators(HwAcc) provide good performance in accelerating computationally intensive applications. In addition, some FPGAs support a dynamic partial reconfig-uration (DPR) techniques to virtualize and share the FPGA underlying hardware resources in time multiplexing during run-time to save resource and power consumption. Integrating FPGA in a cloud environment is an indispensable way to improve efficiency and provide acceleration services to demanding users. More importantly, in recent years it was proved that FPGA resources deployed in …
Smart Monitoring for Semantic Wireless (SCADA/DCS) Systems with Semantic SNMP Protocol.
2015
International audience; n this paper we propose a new implementation of SNMP protocol through (WS) and SOAP protocol, for wireless semantic (SCADA/DCS) systems and (IT-SCADA) platform monitoring. (WS) and SOAP may run on top of secure transport services implemented through protocols like HTTPS combined with industrial protocols as (DNP3, SOAP, ISM BAND, and ZIGBEE).We chose ZIGBBE wireless protocol for implementing our semantic security (IT-SCADA) management platform with semantic SNMP protocol via WS. To detect and infiltrate wireless radio network and semantic attacks, the use of (WS) gateways is needed to include SNMP devices into (WS) based management architecture. The evaluation shows …
NoC based virtualized accelerators as cloud services
2016
National audience; Hardware accelerators(HwAcc) provide good performance in computation intensive applications. Integrating hardware accelerators in a cloud environment is the optimal way to improve the quality of service. However, mapping all possible application statically into the reconfigurable fabric of the FPGA is rather impractical and prohibitively expensive in terms of resource and power consumption. This problem can be alleviated via time multiplexing the access to the underlying hardware resources, FPGA, by designing dynamically reconfigurable accelerators in the cloud. Similarly, the connection and communication between the accelerators and the reconfigurable control will not be…
A new system for watermarking based on the turbo-codes and wavelet 5/3
2012
International audience; In order to contribute to the security, transmission and sharing of medical data between hospital centers, we propose a watermarking scheme for hiding medical information, specific to the patient, in the host image. In this regard, the watermark consists of inserting data (usually binary data) in media (image in our case) and try to find these data with maximum fidelity, after applying various attacks. The principal goal of our proposal is the conservation of psychovisual quality of the image, on the one hand, and the extraction of the different data inserted in another side The robustness of the proposed scheme is tested against various attacks such as JPEG compress…
SECURITY FOR INDUSTRIAL AUTOMATION AND CONTROL SYSTEMS
2013
International audience
Security Wireless Solution for Semantic Smart SCADA/DCS
2015
Journal spécialisé das industrie du gaz; International audience; We present the ability to detect and infiltrate semantic attacks a wireless radio network used in semantic (SCADA/DCS) systems, these attacks deny operators and automated systems the ability to safely and reliably monitor and control semantic sensors, semantic actuators, relays, and breakers. We presented in this work new security semantic wireless protocols as a secure communication support for these modern semantic wireless systems and a global security solution for interconnected (IT-SCADA) platforms.
An efficient FPGA-based architecture for the HEVC intraprediction
2015
National audience; A novel hardware architecture for the High Efficiency Video Coding (HEVC) intra prediction ispresented in this paper, aiming to reduce the computation complexity coming with this moduleand to accelerate the concerned calculations. We propose a new pipelined structure that wenamed Processing Element (PE) to execute all angular modes, and we repeat it in five pathswhich compose our architecture. We propose also another structure perform the Planar mode.This architecture supports all intra prediction modes for all block sizes. The synthesis resultsshow that our solution can run at 213 MHz for FPGA Xilinx Virtex 6 and is capable to processreal time 120 1080p FPS or 30 4K FPS.
High-Level Modeling and Automatic Generation of Dynamically Reconfigurable Systems
2011
International audience; Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on MDE and UML MARTE standard have emerged which aim to simplify the design of complex SoCs. Moreover, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. In parti…