0000000000235502
AUTHOR
B. Desalvo
Nanocrystal memories for FLASH device applications
Nanocrystals memory cells, in which the conventional polysilicon floating gate is replaced by an array of silicon nanocrystals, have been fabricated and characterized. Single cells and cell arrays of 1 Mb and 10 k have been realized by using a conventional 0.15 μm FLASH technology. Si nanocrystals are deposited on top of tunnel oxide by chemical vapor deposition. Properties of the memory cell have been investigated both for NAND and NOR applications in terms of program/erase window and programming times. Suitable program/erase threshold voltage window can be achieved with fast voltage pulses by adequate choice of tunnel and control dielectric. The feasibility of dual bit storage is also pro…
Peculiar aspects of nanocrystal memory cells: Data and extrapolations
Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigate…
Distribution of the threshold voltage window in nanocrystal memories with Si dots formed by chemical vapor deposition: Effect of partial self-ordering
Non volatile memories based on Si nanocrystals (Si-ncs) offer an important alternative to conventional floating gate devices, for the numerous potential advantages associated with the discrete-trap structures [1]. Isolated Si-ncs can be obtained by chemical vapor deposition (CVD) through a fully compatible CMOS process. So far, the main limitation for scaling the CVD Si-nc memories at sub-90 nm node is related to the expected fluctuation, from bit to bit, in the device threshold voltage (VTH), due to the spread in the sur- face fraction (Rdot) covered with Si dots [2]. The reason is the assumption that the dot position and the relative distance are fully random. It will be shown that the nu…