0000000000364745

AUTHOR

Pranav Venkatesh Kulkarni

showing 3 related works from this author

Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization

2018

As the size of the chip is scaling down the density of Intellectual Property (IP) cores integrated on a chip has been increased rapidly. The communication between these IP cores on a chip is highly challenging. To overcome this issue, Network-on-Chip (NoC) has been proposed to provide an efficient and a scalable communication architecture. In the deep sub-micron level NoCs are prone to faults which can occur in any component of NoC. To build a reliable and robust systems, it is necessary to apply efficient fault-tolerant techniques. In this paper, we present a flexible spare core placement in Mesh-of-Tree (MoT) topology using Particle Swarm Optimization (PSO) by considering IP core failures…

020203 distributed computingComputer scienceDistributed computingParticle swarm optimizationTopology (electrical circuits)Fault toleranceHardware_PERFORMANCEANDRELIABILITY02 engineering and technologyNetwork topologyChip020204 information systemsScalabilityHardware_INTEGRATEDCIRCUITS0202 electrical engineering electronic engineering information engineeringBenchmark (computing)Overhead (computing)TENCON 2018 - 2018 IEEE Region 10 Conference
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Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture

2019

In this paper, we propose a two-step fault-tolerant approach to address the faults occurred in cores. In the first stage, a Particle Swarm Optimization (PSO) based approach has been proposed for the fault-tolerant mapping of multiple applications on to the mesh based reconfigurable architecture by introducing spare cores and a heuristic has been proposed for the reconfiguration in the second stage. The proposed approach has been experimented by taking several benchmark applications into consideration. Communication cost comparisons have been carried out by taking the failed cores as user input and the experimental results show that our approach could get improvements in terms of communicati…

010302 applied physicsHeuristic (computer science)business.industryComputer scienceMesh networkingControl reconfigurationParticle swarm optimizationFault tolerance02 engineering and technology01 natural sciences020202 computer hardware & architectureNetwork on a chipSpare partEmbedded system0103 physical sciences0202 electrical engineering electronic engineering information engineeringBenchmark (computing)business
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Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

2018

The increase in the density of the IP cores being fabricated on a chip poses on-chip communication challenges and heat dissipation. To overcome these issues, Network-onChip (NoC) based communication architecture is introduced. In the nanoscale era NoCs are prone to faults which results in performance degradation and un-reliability. Hence efficient fault-tolerant methods are required to make the system reliable in contrast to diverse component failures. This paper presents a flexible spare core placement in torus topology based faulttolerant NoC design. The communications related to the failed core is taken care by selecting the best position for a spare core in the torus network. By conside…

020203 distributed computingComputer scienceParticle swarm optimizationFault toleranceTopology (electrical circuits)Hardware_PERFORMANCEANDRELIABILITY02 engineering and technologyChipTopology020202 computer hardware & architectureReduction (complexity)Network on a chipSpare part0202 electrical engineering electronic engineering information engineeringMetaheuristic
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