0000000000901942
AUTHOR
Salvatore Micalizio
showing 2 related works from this author
Phase Noise and Frequency Stability of the Red-Pitaya Internal PLL
2019
In field-programmable gate array platforms, the main clock is generally a low-cost quartz oscillator whose stability is of the order of $10^{-9}$ to $10^{-10}$ in the short term and $10^{-7}$ to $10^{-8}$ in the medium term, with the uncertainty of tens of ppm. Better stability is achieved by feeding an external reference into the internal phase-locked loop (PLL). We report the noise characterization of the internal PLL of Red-Pitaya platform, an open-source embedded system architected around the Zynq 7010 System on Chip, with analog-to-digital and digital-to-analog converters. Our experiments show that, providing an external 10-MHz reference, the PLL exhibits a residual frequency stability…
Noise characterization of analog to digital converters for amplitude and phase noise measurements
2017
International audience; Improvements on electronic technology in recent years have allowed the application of digital techniques in phase noise metrology where low noise and high accuracy are required, yielding flexibility in systems implementation and setup. This results in measurement systems with extended capabilities, additional functionalities and ease of use. In most digital schemes the Analog to Digital Converters (ADCs) set the ultimate performance of the system, therefore the proper selection of this component is a critical issue. Currently, the information available in literature describes in depth the ADC features only at frequency offsets far from the carrier. However, the perfo…