6533b821fe1ef96bd127c193

RESEARCH PRODUCT

Design methods of multithreaded architectures for multicore microcontrollers

Horia V. CapritaMircea Popa

subject

Instruction setMicrocontrollerMulti-core processorComputer architectureComputer scienceMultithreadingContext (language use)ElectronicsComputer multitaskingComputerSystemsOrganization_PROCESSORARCHITECTURESTemporal multithreading

description

The development of electronic technology today has allowed the implementation of complex architectures, which led to the emergence of multicore processors technology. Multicore architectures are built from superscalar and multithreaded processors. Integrating new technologies in embedded applications requires the development of multicore processors that can be integrated into a smaller area like a classic microcontroller. These processors must manage fewer resources and be able to manage multiple tasks simultaneously. In this paper we present a method of modeling, simulation and evaluation of two multithreaded architectures with limited resources, which could be integrated into embedded systems: Interleaved multithreading (IMT) and Blocked multithreading (BMT). Both techniques permit the processing of multiple independent threads, concurrently. In this paper we propose a SimpleScalar Interleaved Multithreading architecture (SS-IMT) and a SimpleScalar Blocked Multithreading architecture (SS-BMT) that are derived from SimpleScalar simulator. We will evaluate the performances of these architectures compared to the performance of standard SimpleScalar architecture.

yearjournalcountryeditionlanguage
2011-05-012011 6th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI)
https://doi.org/10.1109/saci.2011.5873041