6533b86cfe1ef96bd12c8c27

RESEARCH PRODUCT

Design of MOS Current Mode Logic Gates – Computing the Limits of Voltage Swing and Bias Current

G. Caruso

subject

Power–delay productEmitter coupled logic circuitsBiasingSwingCMOS integrated circuitsComputer Science::Hardware Architecturemode logicComputer Science::Emerging TechnologiesLogic synthesisParasitic capacitanceControl theoryLogic gateHardware_INTEGRATEDCIRCUITSCurrent-mode logicHardware_LOGICDESIGNVoltageMathematics

description

Minimizing a quality metric for an MCML gate, such as power-delay product or energy-delay product, requires solving a system of nonlinear equations subject to constraints on both bias current and voltage swing. In this paper, we will show that the limits of the swing and the bias current are affected by the constraints on maximum area and maximum delay. Moreover, methods for computing such limits are presented.

yearjournalcountryeditionlanguage
2005-07-272005 IEEE International Symposium on Circuits and Systems
https://doi.org/10.1109/iscas.2005.1465916