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RESEARCH PRODUCT

Efficient FPGA Implementation of an Adaptive Noise Canceller

A. ScaglioneC. GiaconiaA. Di Stefano

subject

Computer scienceBandwidth (signal processing)Real-time computingSignal synthesisElectroencephalographyBioelectric potentialsLeast mean squares filterSignal-to-noise ratioGate countError analysisElectronic engineeringHardware_ARITHMETICANDLOGICSTRUCTURESField-programmable gate arrayEvoked PotentialsActive noise control

description

A hardware implementation of an adaptive noise canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the least mean square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel adaptive noise canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.

yearjournalcountryeditionlanguage
2006-10-11
10.1109/camp.2005.22http://hdl.handle.net/10447/18294