Search results for " FPGA"

Design Space Exploration of Parallel Embedded Architectures for Native Clifford Algebra Operations

2012

In the past few decades, Geometric or Clifford algebra (CA) has received a growing attention in many research fields, such as robotics, machine vision and computer graphics, as a natural and intuitive way to model geometric objects and their transformations. At the same time, the high dimensionality of Clifford algebra and its computational complexity demand specialized hardware architectures for the direct support of Clifford data types and operators. This paper presents the design space exploration of parallel embedded architectures for native execution of four-dimensional (4D) and five-dimensional (5D) Clifford algebra operations. The design space exploration has been described along wit…

An FPGA Implementation of a Quadruple-Based Multiplier for 4D Clifford Algebra

2008

Geometric or Clifford algebra is an interesting paradigm for geometric modeling in fields as computer graphics, machine vision and robotics. In these areas the research effort is actually aimed at finding an efficient implementation of geometric algebra. The best way to exploit the symbolic computing power of geometric algebra is to support its data types and operators directly in hardware. However the natural representation of the algebra elements as variable-length objects causes some problems in the case of a hardware implementation. This paper proposes a 4D Clifford algebra in which the variable-length elements are mapped into fixed-length elements (quadruples). This choice leads to a s…

Embedded Coprocessors for Native Execution of Geometric Algebra Operations

2016

Clifford algebra or geometric algebra (GA) is a simple and intuitive way to model geometric objects and their transformations. Operating in high-dimensional vector spaces with significant computational costs, the practical use of GA requires dedicated software and/or hardware architectures to directly support Clifford data types and operators. In this paper, a family of embedded coprocessors for the native execution of GA operations is presented. The paper shows the evolution of the coprocessor family focusing on the latest two architectures that offer direct hardware support to up to five-dimensional Clifford operations. The proposed coprocessors exploit hardware-oriented representations o…

A Programmable Networked Processing Node for 3D Brain Vessels Reconstruction

2011

Real-time 3D imaging represents a developing trend in medical imaging. However, most of the 3D medical imaging algorithms are computationally intensive. In this paper, a programmable networked node for 3D brain vessels reconstruction is proposed. Starting from 2D PC-MRA (Phase-Contrast Magnetic Resonance Angiography) sequences, the node is able to generate the 3D brain vasculature using the MIP (Maximum Intensity Projection) algorithm. The node has been prototyped on the Celoxica RC203E board, equipped with a Virtex II FPGA, to get the advantages of an hardware implementation, reaching a better throughput with respect to analogous software implementations. Its generality and programmable ca…

A Software Defined Radio Platform Implementing a WiFi and ZigBee Receiver

2006

A successful attempt to design and implement a multi-standard compliant Basebnd Processor is here presented. By exploiting the potential of FPGA's reconfigurability, the received signal from RF stage have been processed in order to properly decode frames of IEEE 802.11 (WiFi) and IEEE 802.15.4 (ZigBee) protocols. both falling within the ISM band (centered at 2.45GHz). The experimental implementation carried out is a practical demonstration of the Software Defined Radio concept.

Switching Frequency Effects on the Efficiency and Harmonic Distortion in a Three-Phase Five-Level CHBMI Prototype with Multicarrier PWM Schemes: Expe…

2022

The current climatic scenario requires the use of innovative solutions to increase the production of electricity from renewable energy sources. Multilevel Power Inverters are a promising solution to improve the penetration of renewable energy sources into the electrical grid. Moreover, the performance of MPIs is a function of the modulation strategy employed and of its features (modulation index and switching frequency). This paper presents an extended and experimental analysis of three-phase five-level Cascaded H-Bridges Multilevel Inverter performance in terms of efficiency and harmonic content considering several MC PWM modulation strategies. In detail, the CHBMI performance is analyzed …

Experimental Comparative Analysis of Efficiency and THD for a Three-phase Five-level Cascaded H-Bridge Inverter Controlled by Several MC-PWM Schemes

2021

Cascaded H-Bridges Multilevel Inverters are an innovative and promising solution in different application fields. This topology allows obtaining an improvement in the performance (e.g. reduced harmonic content, the low voltage stress on power components, and high efficiency) in respect to the traditional two-level inverters. In this context, the Multicarrier-PWM strategies play an important role thanks to their features. This paper presents an experimental investigation on the performance of a three-phase five-level Cascaded H-Bridge inverter by using different PWM modulation strategies. In particular, the paper is focused on the experimental validation of the main features of Multicarrier …

Dynamic performance evaluation of a non linear digital control technique for multiphase VRMs

2010

Biometric sensors rapid prototyping on field-programmable gate arrays

2015

AbstractBiometric user authentication in large-scale distributed systems involves passive scanners and networked workstations and databases for user data acquisition, processing, and encryption. Unfortunately, traditional biometric authentication systems are prone to several attacks, such as Replay Attacks, Communication Attacks, and Database Attacks. Embedded biometric sensors overcome security limits of conventional software recognition systems, hiding its common attack points. The availability of mature reconfigurable hardware technology, such as field-programmable gate arrays, allows the developers to design and prototype the whole embedded biometric sensors. In this work, two strong an…

NoC based virtualized FPGA as cloud Services

2016

International audience; Web-based applications are increasingly demanding many computationally intensive services. On the other hand, FPGA-based hardware accelerators(HwAcc) provide good performance in accelerating computationally intensive applications. In addition, some FPGAs support a dynamic partial reconfig-uration (DPR) techniques to virtualize and share the FPGA underlying hardware resources in time multiplexing during run-time to save resource and power consumption. Integrating FPGA in a cloud environment is an indispensable way to improve efficiency and provide acceleration services to demanding users. More importantly, in recent years it was proved that FPGA resources deployed in …