Search results for " arch"
showing 10 items of 7915 documents
Isothermal relaxation of discommensurations in K2ZnCl4
1994
At the incommensurate-ferroelectric transition temperature T c of K 2 ZnCl 4 , the dielectric susceptibility contains an anomalous contribution both above and below T c . Previous quasi-static dielectric measurements and hysteresis loops demonstrated that this anomalous part arises from the peculiar dynamics of discommensurations. We have used isothermal dielectric measurements to get some insight into the long time dynamics of these discommensurations. We have found that the characteristic relaxation times τ are of the order of 10 4 s in the incommensurate and in the ferroelectric phase. Even more unusual is a non-monotonous relaxation which is observed in a restricted temperature range ab…
Domain Walls Motions in Barium Titanate Ceramics
1996
The shear modulus and mechanical loss at low frequencies (0.01, 0.3, 1 Hz) are measured by an inverted pendulum for BaTiO 3 ceramic with large grain sizes. The permittivity and dielectric losses are also investigated for the same material at higher frequencies between 1 and 100 kHz as function of temperature. Those results show several relaxation peaks in the ferroelectric phases. The activation energy of each peak is obtained to be 0.29, 0.45, 0.68, 0.92 eV. The influences of strain amplitude and thermal treatments are studied specially for the mechanical relaxation peak located in the tetragonal phase. All the relaxation peaks could be associated to the interaction of oxygen vacancies in …
Non-Linearity Extremum in Niobium Doped Potassium Tantalate
1997
We report non-linear dielectric measurements in the KTaO 3 :Nb system (x Nb ≤ 0.05). The non-linear susceptibility diverges at low temperatures and reaches maximum values in the intermediate range (0.0075 ≤ x Nb ≤ 0.02). To account for this extremum non linearity, we propose a model of temperature dependent clusters which fits with a number of experimental reports. We also suggest that this model may be applied to the related compounds SrTiO 3 :Ca and KTaO 3 :Na.
Identification of parameters and harmonic losses of a deep-bar induction motor
2017
High frequency harmonics from a frequency converter causes additional losses in a deep-bar induction motor. The harmonics have their own amplitude and phase with respect to the fundamental signal, but the harmonic loss is only dependent on the amplitude of harmonics. A deep-bar induction motor can be modelled by a triple-cage circuit to take skin effect into account. The triple cage circuit having many parameters could be estimated from a small-signal model of the machine by using Differential Evolution. The correctly estimated parameters make the triple-cage circuit valid in a wide range of frequencies. However, the triple-cage circuit is very complicated which makes it difficult to model …
Transport properties of Bi2Sr2Ca2Cu3O10+δ Bicrystal Grain Boundary Josephson Junctions and SQUIDs
1996
Josephson junctions and SQUIDs on 36.8° SrTiO 3 bicrystal substrates were prepared from epitaxial Bi 2 Sr 2 Ca 2 Cu 3 O 10+δ thin films with critical temperatures around 95K. The current-voltage characteristics are well described by the resistively and capacitively shunted junction model. I c R n products of 50μV at 77K and 0.7mV at 4.2K have been reached. The I c (B) dependence is symmetric to B = 0 with an I c suppression of 90% in the first minimum. Nevertheless it turns out, that the junctions are inhomogeneous on a μm scale. SQUID modulations observed at 78K indicate a flux-voltage transfer function of 2.7μV/Φ 0 at this temperature.
Online Management of Hybrid DRAM-NVMM Memory for HPC
2019
Non-volatile main memories (NVMMs) offer a comparable performance to DRAM, while requiring lower static power consumption and enabling higher densities. NVMM therefore can provide opportunities for improving both energy efficiency and costs of main memory. Previous hybrid main memory management approaches for HPC either do not consider the unique characteristics of NVMMs, depend on high profiling costs, or need source code modifications. In this paper, we investigate HPC applications' behaviors in the presence of NVMM as part of the main memory. By performing a comprehensive study of HPC applications and based on several key observations, we propose an online hybrid memory architecture for …
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
2010
The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge.In this paper, uLBDR (Universal Logic-Based Distributed Routing) is proposed as an efficient logic-based mechanism that adapts to any irregular topology derived from 2D meshes, being an alter…
Towards Open Domain Chatbots—A GRU Architecture for Data Driven Conversations
2018
Understanding of textual content, such as topic and intent recognition, is a critical part of chatbots, allowing the chatbot to provide relevant responses. Although successful in several narrow domains, the potential diversity of content in broader and more open domains renders traditional pattern recognition techniques inaccurate. In this paper, we propose a novel deep learning architecture for content recognition that consists of multiple levels of gated recurrent units (GRUs). The architecture is designed to capture complex sentence structure at multiple levels of abstraction, seeking content recognition for very wide domains, through a distributed scalable representation of content. To …
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology
2010
Nowadays, system designers have adopted Networks-on-Chip as communication infrastructure of general-purpose tile-based Multi-Processor System-on-Chip (MPSoC). Such decision implies that a certain topology has to be selected to efficiently interconnect many cores on the chip. To ease such a choice, the networking literature offers a plethora of works about topology analysis and characterization for the off-chip domain. However, theoretical parameters and many intuitive assumptions of such off-chip networks do not necessarily hold when a topology is laid out on a 2D silicon surface. This is due to the distinctive features of silicon technology design pitfalls. This work is a first milestone t…
Real-time signal processing in embedded systems
2016
International audience