Search results for " architect"

Multiprocessor SoC Implementation of Neural Network Training on FPGA

2008

Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for gr…

A Communication-Aware Topological Mapping Technique for NoCs

2008

Networks---on---Chip (NoCs) have been proposed as a promising solution to the complex on-chip communication problems derived from the increasing number of processor cores. The design of NoCs involves several key issues, being the topological mapping (the mapping of the Intellectual Properties (IPs) to network nodes) one of them. Several proposals have been focused on topological mapping last years, but they require the experimental validation of each mapping considered. In this paper, we propose a communication-aware topological mapping technique for NoCs. This technique is based on the experimental correlation of the network model with the actual network performance, thus avoiding the need…

Analysis of Interconnected Earthing Systems of MV/LV Substations in Urban Areas

2008

The paper proposes a study of the fault current distribution in an extended interconnection of earthing systems, belonging to secondary substations, during a single-line-to-earth fault. By applying the analysis methodology defined by the same authors in some previous works, the paper shows how the value of some important geometrical and electrical parameters of a MV network can influence the value of the earth current at the fault location.

Domain-Knowledge Optimized Simulated Annealing for Network-on-Chip Application Mapping

2013

Network-on-Chip architectures are scalable on-chip interconnection networks. They replace the inefficient shared buses and are suitable for multicore and manycore systems. This paper presents an Optimized Simulated Annealing (OSA) algorithm for the Network-on-Chip application mapping problem. With OSA, the cores are implicitly and dynamically clustered using knowledge about communication demands. We show that OSA is a more feasible Simulated Annealing approach to NoC application mapping by comparing it with a general Simulated Annealing algorithm and a Branch and Bound algorithm, too. Using real applications we show that OSA is significantly faster than a general Simulated Annealing, withou…

Application of information fusion to unreliable wireless sensor networks

2012

Masteroppgave i informasjons- og kommunikasjonsteknologi IKT590 2012 – Universitetet i Agder, Grimstad Thesis is appropriated analyze to performance metric evaluation for decentralized distributed detection sensor network strategy. Performance metric investigated a typical wireless sensor network with respect to IEEE 802.15.4 standard. Distributed detection is considered with present of the fusion node as long as clustering and non-clustering sensor network. The clusters are organized uniform and non-uniform topology sensor networks with tree-based topologies and hierarchical multi-level fusion centers. Fusion centers are acting as head of cluster for decision making based on majority-like …

Automatic construction of test sets: Theoretical approach

2005

We consider the problem of automatic construction of complete test set (CTS) from program text. The completeness criterion adopted is C1, i.e., it is necessary to execute all feasible branches of program at least once on the tests of CTS. A simple programming language is introduced with the property that the values used in conditional statements are not arithmetically deformed. For this language the CTS problem is proved to be algorithmically solvable and CTS construction algorithm is obtained. Some generalizations of this language containing counters, stacks or arrays are considered where the CTS problem remains solvable. In conclusion the applications of the obtained results to CTS constr…

DRESS: A Distributed RMS Evaluation Simulation Software

2020

Distributed environments consist of a huge number of entities that cooperate to achieve complex goals. When interactions occur between unknown parties, intelligent techniques for estimating agent reputations are required. Reputation management systems (RMS's) allow agents to perform such estimation in a cooperative way. In particular, distributed RMS's exploit feedbacks provided after each interaction and allow prediction of future behaviors of agents. Such systems, in contrast to centralized RMSs, are sensitive to fake information injected by malicious users; thus, predicting the performance of a distributed RMS is a very challenging task. Although many existing works have addressed some c…

A GPU-Based DVC to H.264/AVC Transcoder

2010

Mobile to mobile video conferencing is one of the services that the newest mobile network operators can offer to users With the apparition of the distributed video coding paradigm which moves the majority of complexity from the encoder to the decoder, this offering can be achieved by introducing a transcoder This device has to convert from the distributed video coding paradigm to traditional video coding such as H.264/AVC which is formed by simpler decoders and more complex encoders, and allows to the users to execute only the low complex algorithms In order to deal with this high complex video transcoder, this paper introduces a graphics processing unit based transcoder as base station The…

EvoStar 2019: Bio-Inspired Computing and Automation

2020

A Visual Simulation Framework For Simultaneous Multithreading Architectures

2011

The computing systems, and particularly microarchitectures, are in a continuous expansion reaching an unmanageable complexity by the human mind. In order to understand and control this expansion, researchers need to design and implement larger and more complex systems’ simulators. In the current paradigm the simulators play the key role in going further, by translating all complex processing mechanisms in relevant and easy to understand information. This paper aims to make a suggestive description of the concepts and principles implemented into a Simultaneous Multithreading Architecture. We introduce the SMTAHSim framework, an educational tool that simulates in an interactive manner the imp…