Search results for " hardware"
showing 10 items of 422 documents
A preliminary study of agility in business and production - Cases of early-stage hardware startups
2018
[Context] Advancement in technologies, popularity of small-batch manufacturing and the recent trend of investing in hardware startups are among the factors leading to the rise of hardware startups nowadays. It is essential for hardware startups, companies that involve both software and hardware development, to be not only agile to develop their business but also efficient to develop the right products. [Objective] We investigate how hardware startups achieve agility when developing their products in early stages. [Methods] A qualitative research is conducted with data from 20 hardware startups. [Result] Preliminary results show that agile development is known to hardware entrepreneurs, howe…
Improvement of Fingerprint Sensor Reading Using FPGA Devices
2008
In order to realize fingerprint recognition system in real time environment, we describe in this paper signal controller to read fingerprint sensor generated in FPGA devices. Basically this signal is generated using state machine. The simulation result for behavioral simulation and signal generation read by logic analyzer are presented in this paper. Initialization and reading time for 76800 pixels are 50.99 mS. It is faster than fingerprint sensor using USB connection, which is more than 250 ms.
Hardware-efficient matrix inversion algorithm for complex adaptive systems
2012
This work shows an FPGA implementation for the matrix inversion algebra operation. Usually, large matrix dimension is required for real-time signal processing applications, especially in case of complex adaptive systems. A hardware efficient matrix inversion procedure is described using QR decomposition of the original matrix and modified Gram-Schmidt method. This works attempts a direct VHDL description using few predefined packages and fixed point arithmetic for better optimization. New proposals for intermediate calculations are described, leading to efficient logic occupation together with better performance and accuracy in the vector space algebra. Results show that, for a relatively s…
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems
2017
Paper presented at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), held in Baltimore, MD, USA, on 28-31 May 2017.
Hardware implementation of content based video indexing algorithms
2005
This paper focus on hardware implementation of content based video indexing techniques by using the FPGA technology. We aim to propose hardware modules that can satisfy requirements of constrained applications, such as real time applications and complex applications that can combine a large number of techniques in the same indexing system. We represent tow examples of micro-architectures related to the dominant colors descriptor and the compact color descriptor.
Concept of virtual machine based high resolution display wall
2014
This paper presents the scalability and hardware dependency problems found in existing solutions in the high resolution display wall domain and proposes a new solution. Authors propose hosting the system that provides the visual content for the display wall inside a virtual machine. In such way any needed configuration of displays and resolutions can be applied to the graphics processing unit simulated by the virtualization system. The frame buffer content of the virtual graphics processing unit is then split, encoded with H.264 and sent over gigabit Ethernet as an RTP stream to the display wall. The display wall is driven by Raspberry Pi embedded devices that receive the stream, decode it …
Hardware implementation of real-time Extreme Learning Machine in FPGA: Analysis of precision, resource occupation and performance
2016
Extreme Learning Machine (ELM) on-chip learning is implemented on FPGA.Three hardware architectures are evaluated.Parametrical analysis of accuracy, resource occupation and performance is carried out. Display Omitted Extreme Learning Machine (ELM) proposes a non-iterative training method for Single Layer Feedforward Neural Networks that provides an effective solution for classification and prediction problems. Its hardware implementation is an important step towards fast, accurate and reconfigurable embedded systems based on neural networks, allowing to extend the range of applications where neural networks can be used, especially where frequent and fast training, or even real-time training…
A platform for the development and the validation of HW IP components starting from reference software specifications
2008
Abstract Signal processing algorithms become more and more efficient as a result of the developments of new standards. It is particularly true in the field video compression. However, at each improvement in efficiency and functionality, the complexity of the algorithms is also increasing. Textual specifications, that in the past were the original form of specifications, have been substituted by reference software which became the starting point of any design flow leading to implementation. Therefore, designing an embedded application has become equivalent to port a generic software on a, possibly heterogeneous, embedded platform. Such operation is getting more and more difficult because of …
Sliding Mode Control of Quadratic Boost Converters Based on Min-Type Control Strategy
2023
The paper deals with the control of a quadratic boost converter supplied by low-voltage energy sources, such as photovoltaic panels, fuel cells, or batteries. The control scheme consists of two control loops. A min-type controller governs the inner loop to force the current state of the nominal model to converge in a neighborhood of the equilibrium state. The external loop processes the output tracking error using an integrator, and it allows reconfiguring the converter's working point by changing the equilibrium state given in the input to the internal loop. This configuration assures both zero tracking error of the output voltage and robustness against load and input voltage variations an…
On the Use of GPU for Accelerating Communication-Aware Mapping Techniques
2015
Different communication-aware mapping techniques were proposed in recent years for improving the performance of distributed systems based on both, off-chip and on-chip networks. Some of these proposals were based on heuristic search for finding pseudo-optimal assignments of tasks and processing elements. However, the technology integration improvements have allowed a significant increase in the number of network nodes, requiring the acceleration of the heuristic search. In this paper, we propose a comparative study of the local search method used in a communication-aware mapping technique, when implemented on different parallel architectures. We compare the performance provided by a version…