Search results for "Computer hardware"
showing 10 items of 378 documents
The ATLAS TileCal read-out drivers signal reconstruction
2009
TileCal is the hadronic calorimeter of the ATLAS experiment at the LHC collider at CERN. The Read-Out Drivers (ROD) are the core of the off-detector electronics. The main components of the RODs are the Digital Signal Processor (DSP) placed on the Processing Unit (PU) dautherboards. This paper describes the DSP code and its performance with calibration and real data. The code is divided into two different parts: the first part contains the core functionalities and the second one the reconstruction algorithms. The core acts as an operating system and it controls the configuration, the data reception, transmission, online monitoring and the synchronization between front-end data and the Trigge…
Locust: C++ software for simulation of RF detection
2019
The Locust simulation package is a new C++ software tool developed to simulate the measurement of time-varying electromagnetic fields using RF detection techniques. Modularity and flexibility allow for arbitrary input signals, while concurrently supporting tight integration with physics-based simulations as input. External signals driven by the Kassiopeia particle tracking package are discussed, demonstrating conditional feedback between Locust and Kassiopeia during software execution. An application of the simulation to the Project 8 experiment is described. Locust is publicly available at https://github.com/project8/locust_mc.
ATLAS SemiConductor Tracker: operation and performance
2011
The SemiConductor Tracker (SCT) is a silicon strip detector and one of the key precision tracking devices in the Inner Detector of the ATLAS (A Toroidal LHC ApparatuS) experiment at CERN. The SCT installation in the ATLAS experimental cavern was completed in 2007 and it has been operational since then. An extensive commissioning phase followed, during which calibration data was collected and the performance of the system was studied. The SCT was ready for the first LHC proton-proton collisions and it continues recording data successfully since then. In this paper, the current status, operation and performance of the SCT is reviewed, including results from data-taking periods in 2010 and 201…
THE FASTBUS READ-OUT SYSTEM FOR THE ALEPH TIME PROJECTION CHAMBER
1989
The readout system for the Aleph central tracking detector, a large time projection chamber (TPC), consists of more than 100 FASTBUS crates with approximately 1000 FASTBUS modules. The detector and its associated electronics are briefly presented, followed by a more detailed description of the readout and control system. The discussion covers the sector readout, electronics calibration, front-end data acquisition, data pipelining, and service request handling. Experiences with the system are discussed. >
The read-out processors of the Aleph time projection chamber and their performance
1990
The Aleph detector is installed on the LEP electron-positron storage ring. Its central tracking detector, a time projection chamber (TPC), has about 50000 channels of sampling electronics. The digitized signals are processed by 72 double-width Fastbus modules built around an MC 68020 processor. The time projection processor is described, and the solutions, both hardware and software, adopted to run and manage such a complex system in a Fastbus-VAX environment are discussed. Practical experience with the system is reported. >
DSP Online Algorithms for The ATLAS TileCal Read-Out Drivers
2007
TileCal is the hadronic tile calorimeter of the ATLAS experiment at LHC/CERN. The central element of the back-end system of the TileCal detector is the read-out driver (ROD).The main components of the TileCal ROD are the digital signal processors (DSPs) placed on the processing unit (PU) daughterboards. This paper presents a detailed description of the code developed for the DSPs. The code is divided into two different parts: the first part contains the core functionalities and the second part the reconstruction algorithms. The core acts as an operating system and controls configuration, data reception and transmission and synchronization between front-end data and the timing, trigger and c…
Pre-production validation of the ATLAS level-1 calorimeter trigger system
2006
The Level-1 Calorimeter Trigger is a major part of the first stage of event selection for the ATLAS experiment at the LHC. It is a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of trigger objects and energy sums. Prototypes of all module types have been undergoing intensive testing before final production during 2005. Verification of their correct operation has been performed stand-alone and in the ATLAS test-beam at CERN. Results from these investigations will be presented, along …
Construction, test and commissioning of the triple-gem tracking detector for compass
2002
The Small Area Tracking system of the COMPASS experiment at CERN includes a set of 20 large area, fast position-sensitive Gas Electron Multiplier (GEM) detectors, designed to reliably operate in the harsh radiation environment of the experiment. We describe in detail the design, choice of materials, assembly procedures and quality controls used to manufacture the devices. The test procedure in the laboratory, the performance in test beams and in the initial commissioning phase in the experiment are presented and discussed.
ATLAS level-1 calorimeter trigger: subsystem tests of a Jet/Energy-sum Processor module
2003
The ATLAS Level-1 Calorimeter Trigger consists of a Preprocessor, a Cluster Processor (CP), and a Jet/Energy-sum Processor (JEP). The CP and JEP receive digitised trigger-tower data from the Preprocessor and produce trigger multiplicities and total and missing energy for the final trigger decision. The trigger will also provide region-of-interest (RoI) information for the Level-2 trigger and intermediate results of the data acquisition (DAQ) system for monitoring and diagnostics by using readout driver modules (ROD). The Jet/Energy-sum Processor identifies and localises jets, and sums total and missing transverse energy information from the trigger data. The Jet/Energy Module (JEM) is the m…
Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs
2014
Abstract The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100 ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R&D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20 ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and …