Search results for "Computer hardware"
showing 10 items of 378 documents
Design of the online PC farm for the high level trigger of the NA62 experiment at CERN
2012
We present a highly efficient data processing framework optimized for software based triggers of fixed-target HEP experiments with continuous data collection during burst time alternating with longer out-of-burst periods.
High Performance FOC for Induction Motors with Low Cost ATSAM3X8E Microcontroller
2018
In this paper the Authors present the Arduino Due board application for an induction motor field oriented control (FOC) algorithm. The low cost Arduino Due board is equipped with a ATSAM3X8E microcontroller that performs the algorithm calculation, data processing, current signals and speed/position data acquisition. The control algorithm has been developed with the help of the open source Arduino integrated development environment, whereas a user friendly control interface, used to manage the speed or position set point, has been developed in Java language by means of an other open source software, namely, Processing. An experimental test bed has been set up in order to validate the FOC sys…
The Belle II Pixel Detector Data Acquisition and Background Suppression System
2017
The Belle II experiment at the future SuperKEKB collider in Tsukuba, Japan, features a design luminosity of 8 1035 cm−2s−1, which is a factor of 40 larger than that of its predecessor Belle. The pixel detector (PXD) with about 8 million pixels is based on the DEPFET technology and will improve the vertex resolution in beam direction by a factor of 2. With an estimated trigger rate of 30 kHz, the PXD is expected to generate a data rate of 20 GBytes/s, which is about 10 times larger than the amount of data generated by all other Belle II subdetectors. Due to the large beam-related background, the PXD requires a data acquisition system with high-bandwidth data links and realtime background red…
Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC
2015
[EN] The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a View the MathML source window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the tota…
Optimisation of direct digital frequency synthesisers based on CORDIC
2001
Methods to simplify digital frequency synthesizers based on the co-ordinate rotation digital computer (CORDIC) algorithm are presented. Application of these methods leads to performance enhancement, compared with the topologies previously proposed in the literature. For a given output precision, hardware resources are reduced and spur-free dynamic range is increased.
Performance of the Fully Digital FPGA-Based Front-End Electronics for the GALILEO Array
2014
In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. The digital processing of the data from the GALILEO germanium detectors has demonstrated the capability to achieve an energy resolution of 1.53 per mil at an energy of 1.33 MeV.
Muon identification with the ATLAS Tile Calorimeter Read-Out Driver for Level-2 trigger purposes
2008
The Hadronic Tile Calorimeter (TileCal) at the ATLAS experiment is a detector made out of iron as passive medium and plastic scintillating tiles as active medium. The light produced by the particles is converted to electrical signals which are digitized in the front-end electronics and sent to the back-end system. The main element of the back-end electronics are the VME 9U Read-Out Driver (ROD) boards, responsible of data management, processing and transmission. A total of 32 ROD boards, placed in the data acquisition chain between Level-1 and Level-2 trigger, are needed to read out the whole calorimeter. They are equipped with fixed-point Digital Signal Processors (DSPs) that apply online …
Computing the Probability for Data Loss in Two-Dimensional Parity RAIDs
2017
Parity RAIDs are used to protect storage systems against disk failures. The idea is to add redundancy to the system by storing the parity of subsets of disks on extra parity disks. A simple two-dimensional scheme is the one in which the data disks are arranged in a rectangular grid, and every row and column is extended by one disk which stores the parity of it.In this paper we describe several two-dimensional parity RAIDs and analyse, for each of them, the probability for dataloss given that f random disks fail. This probability can be used to determine the overall probability using the model of Hafner and Rao. We reduce subsets of the forest counting problem to the different cases and show…
MAC-Engine
2011
In this demo, we prove that the flexibility supported by off-the-shelf IEEE 802.11 hardware can be significantly extended if we move the control of the MAC programming interface from the driver to the firmware, i.e. from the host CPU to the card CPU. To this purpose, we introduce the concept of MAC--Engine, that is an executor of Programmable Finite State Machines (PFSM) implemented at the firmware level: we show how the card itself can support different protocol logics thanks to PFSM bytecode representations that can be dynamically injected inside the card memory at run-time without incurring in down time issues or network disconnect events. We provide different PFSM examples in order to t…
A novel methodology for accelerating bitstream relocation in partially reconfigurable systems
2012
International audience; Xilinx Virtex FPGAs offer the possibility of Partial Reconfiguration (PR). Arbitrary tasks can be allocated and de-allocated onto FPGA without system interruption. However, mapping a task to any available PR region requires a unique partial bitstream for each partition, hence reducing memory storage requirements. In recent years, an interest on overcoming this problem has lead to the concept of Partial Bitstream Relocation (PBR). The principle is to perform bitstream modification to map it to different regions. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. In order to find the bes…