Search results for "Electrical Circuits"
showing 10 items of 91 documents
Evaluation of an Alternative for Increasing Switch Radix
2011
In large switch-based interconnection networks, increasing the switch radix results in a decrease in the total number of network components. In this paper we evaluate an interesting strategy for building high-radix switches going beyond the integration scale bounds. This approach is independent of the evolution of single-chip switches and will remain valid as integration scale keeps evolving. Simulation results show that with a correct internal switch design, this kind of switches achieves almost the same performance as single-chip switches with the same radix, which would be unfeasible with current integration scale.
2014
This paper deals with the fault detection problem for a class of discrete-time wireless networked control systems described by switching topology with uncertainties and disturbances. System states of each individual node are affected not only by its own measurements, but also by other nodes’ measurements according to a certain network topology. As the topology of system can be switched in a stochastic way, we aim to designH∞fault detection observers for nodes in the dynamic time-delay systems. By using the Lyapunov method and stochastic analysis techniques, sufficient conditions are acquired to guarantee the existence of the filters satisfying theH∞performance constraint, and observer gains…
Global stability of coupled Markovian switching reaction–diffusion systems on networks
2014
Abstract In this paper, we investigate the stability problem for some Markovian switching reaction–diffusion coupled systems on networks (MSRDCSNs). By using the Lyapunov function, we establish some novel stability principles for stochastic stability, asymptotically stochastic stability, globally asymptotically stochastic stability and almost surely exponential stability of the MSRDCSNs. These stability principles have a close relation to the topology property of the network. We also provide a systematic method for constructing global Lyapunov function for these MSRDCSNs by using graph theory. The new method can help analyze the dynamics of complex networks.
A fast heuristic for solving the D1EC coloring problem
2010
In this paper we propose an efficient heuristic for solving the Distance-1 Edge Coloring problem (D1EC) for the on-the-fly assignment of orthogonal wireless channels in wireless as soon as a topology change occurs. The coloring algorithm exploits the simulated annealing paradigm, i.e., a generalization of Monte Carlo methods for solving combinatorial problems. We show that the simulated annealing-based coloring converges fast to a sub optimal coloring scheme even for the case of dynamic channel allocation. However, a stateful implementation of the D1EC scheme is needed in order to speed-up the network coloring upon topology changes. In fact, a stateful D1EC reduces the algorithm’s convergen…
A New ESO-Based Method to Find the Optimal Topology of Structures Subject to Multiple Load Conditions
2014
In the field of topology optimization problems, the Evolutionary Structural Optimization (ESO) method is one of the most popular and easy to use. When dealing with problems of reasonable difficulty, the ESO method is able to give very good results in reduced times and with a limited request of computational resources. Generally, main applications of this method are addressed to the definition of the optimal topology of a component subjected to a single load condition. In this work, a new methodology, based on the ESO approach, is introduced for the study of the optimal topology of a component subjected to multiple load conditions. The new procedure, entirely developed in the APDL programmin…
A heuristic for fast convergence in interference-free channel assignment using D1EC coloring
2010
This work proposes an efficient method for solving the Distance-1 Edge Coloring problem (D1EC) for the assignment of orthogonal channels in wireless networks with changing topology. The coloring algorithm is performed by means of the simulated annealing method, a generalization of Monte Carlo methods for solving combinatorial problems. We show that the simulated annealing-based coloring converges fast to a suboptimal coloring scheme. Furthermore, a stateful implementation of the D1EC scheme is proposed, in which network coloring is executed upon topology changes. The stateful D1EC is also based on simulated annealing and reduces the algorithm’s convergence time by one order of magnitude in …
OLS Identification of network topologies
2011
Abstract In many applications, it is important to derive information about the topology and the internal connections of more dynamical systems interacting together. Examples can be found in fields as diverse as Economics, Neuroscience and Biochemistry. The paper deals with the problem of deriving a descriptive model of a network, collecting the node outputs as time series with no use of a priori insight on the topology. We cast the problem as the optimization of a cost function where a set of parameters are used to operate a trade-off between accuracy and complexity in the final model. The problem of reducing the complexity is addressed by fixing a certain degree of sparsity and finding the…
Voltage Source Multilevel Inverters With Reduced Device Count: Topological Review and Novel Comparative Factors
2021
Multilevel inverters (MLIs) have gained increasing interest for advanced energy-conversion systems due to their features of high-quality produced waveforms, modularity, transformerless operation, voltage, and current scalability, and fault-tolerant operation. However, these merits usually come with the cost of a high number of components. Over the past few years, proposing new MLIs with a lower component count has been one of the most active topics in power electronics. The first aim of this article is to update and summarize the recently developed multilevel topologies with a reduced component count, based on their advantages, disadvantages, construction, and specific applications. Within …
New Multilevel Inverter Topology with Reduced Component Count
2019
This paper introduces a new topology of modular multilevel inverters, being suitable in medium and high voltage applications. As compared to the existing circuits, the proposed topology has advantages of high ‘levels/components’ ratio, increasing the output voltage levels without increasing the voltage stress across the used switches, structure simplicity, isolation features, and modularity. These merits allow it to fit well in high-reliability medium-power applications, which require fast troubleshooting and maintenance flexibility. Operating principles of the proposed scheme are detailed in low frequency and pulse width modulation. Simulation and experimental results validate the effectiv…
Fault-Tolerant Application Mapping on to ZMesh topology based Network-on-Chip Design
2020
This paper proposes Particle Swarm Optimization (PSO) based fault-tolerant application mapping on to ZMesh topology based Network-on-Chip (NoC) design. Permanent faults in application cores has been considered and performed application mapping using PSO. The major contribution of this paper is to find out the best position for the spare core to be placed in the network using PSO. Experimentations have been carried out by scaling the ZMesh network size and percentage of network faults. The results show that the proposed approach leads to minimum overhead in communication cost over fault-free result.