Search results for "Embedded Systems"

showing 10 items of 69 documents

Dispositif d'éclairage homogène

2013

[INFO.INFO-ES]Computer Science [cs]/Embedded Systems[ INFO.INFO-ES ] Computer Science [cs]/Embedded Systems[INFO.INFO-ES] Computer Science [cs]/Embedded Systems
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WiseNET: smart camera network combined with ontological reasoning for smart building management

2016

International audience; Visual sensor networks (VSN) have become a part of our daily life [1] [2]. Based on our experience we have identified two main problems on VSN. Firstly, the problem of selecting relevant information from the huge amount of data given by the network. Secondly, the problem of integrating the information coming from the different nodes of the network, i.e., linking the different informations together in order to take a decision. These problems can be overcome by including smart cameras in charge of extracting the significant information from the scene and by adding contextual semantic information, i.e., semantic information of what the camera observes, building informat…

[INFO.INFO-ES]Computer Science [cs]/Embedded Systems[ INFO.INFO-ES ] Computer Science [cs]/Embedded Systems[INFO.INFO-ES] Computer Science [cs]/Embedded Systems
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IP-XACT and MARTE based approach for partially reconfigurable systems-on-chip.

2011

International audience; Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on MDE and UML MARTE standard have emerged which aim to simplify the design of complex SoCs. Moreover, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. In parti…

[INFO.INFO-ES]Computer Science [cs]/Embedded Systems[ INFO.INFO-ES ] Computer Science [cs]/Embedded Systems[INFO.INFO-ES] Computer Science [cs]/Embedded Systems
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High-Level Modeling and Automatic Generation of Dynamically Reconfigurable Systems

2011

International audience; Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on MDE and UML MARTE standard have emerged which aim to simplify the design of complex SoCs. Moreover, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. In parti…

[INFO.INFO-ES]Computer Science [cs]/Embedded Systems[ INFO.INFO-ES ] Computer Science [cs]/Embedded Systems[INFO.INFO-ES] Computer Science [cs]/Embedded Systems
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A New Development Framework for Multi-Core Processor based Smart-Camera Implementations

2015

International audience; The exponential evolution of the smart camera processing performances is directly linked to the improvements on hardware processing elements. Nowadays, high processing performances can be reached considering hardware targets which enables a high level of task parallelism to be implemented. Highly regular tasks are good candidate for a reconfigurable logic implementation and less regular parts of the algorithm could be described on the processor. Meanwhile the prototyping time is related to the selected target and the associated development methodology. The implementation on reconfigurable logic is highly efficient in exploiting the intrinsic task parallelism neverthe…

[INFO.INFO-ES]Computer Science [cs]/Embedded Systems[ INFO.INFO-ES ] Computer Science [cs]/Embedded Systems[INFO.INFO-ES] Computer Science [cs]/Embedded Systems
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Optimised spatio-temporal descriptors for real-time fall detection : comparison of SVM and Adaboost based classification

2013

International audience; We propose a supervised approach to detect falls in home environment using an optimized descriptor adapted to real-time tasks. We introduce a realistic dataset of 222 videos, a new metric allowing to evaluate fall detection performance in a video stream, and an automatically optimized set of spatio-temporal descriptors which fed a supervised classifier. We build the initial spatio-temporal descriptor named STHF using several combinations of transformations of geometrical features (height and width of human body bounding box, the user's trajectory with her/his orientation, projection histograms, and moments of orders 0, 1, and 2). We study the combinations of usual tr…

[INFO.INFO-ES]Computer Science [cs]/Embedded Systems[ INFO.INFO-ES ] Computer Science [cs]/Embedded Systems[INFO.INFO-ES] Computer Science [cs]/Embedded Systems
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Predicting spread patterns of centrifugal fertiliser spreaders

2014

International audience; Nowadays farmers recognize the importance of a correct and precise fertiliser application: non-uniform spread patterns cause extra pressure on the environment and might result in economic losses for the farmer. In Europe most spreading is done by centrifugal fertilizer spreaders but their spreading process is not easy to monitor and to control. To perform a precise fertilising farmers need proper tools to determine and evaluate the spread pattern at farm level. Therefore the Flemish Institute for Agricultural and Fisheries Research (ILVO) is exploring and developing a fast and accurate technique for measuring the spread pattern of conventional centrifugal spreaders. …

[SDE] Environmental Sciences[SDV]Life Sciences [q-bio]spread patternimage techniques[INFO.INFO-ES] Computer Science [cs]/Embedded Systemsballistic flight;fertiliser[SDV] Life Sciences [q-bio][SDE]Environmental Sciences[SDV.BV]Life Sciences [q-bio]/Vegetal Biologycross correlation[SDV.BV] Life Sciences [q-bio]/Vegetal Biology[INFO.INFO-ES]Computer Science [cs]/Embedded Systems[ INFO.INFO-ES ] Computer Science [cs]/Embedded SystemsComputingMilieux_MISCELLANEOUS
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Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: a XILINX EDK case study

2012

International audience; In this paper we present framework for the deployment of hardware IPs at high-levels of abstraction. It is based in a model- driven approach that aims at the automatic generation of Dynamic Partial Reconfiguration designs created in Xilinx Platform Studio (XPS). Contrary to previous approaches, we make use of the IP-XACT standard to facilitate the deployment of hardware IPs, their parameterization and subsequent integration. We propose an extension to the MARTE profile for IP deployment, and we introduce the necessary model transformations to obtain a high- level representation from an IP-XACT component library. These models are then used to create a platform in MART…

business.industryComputer science020208 electrical & electronic engineeringHardware description languageControl reconfiguration020206 networking & telecommunications02 engineering and technology[INFO.INFO-ES] Computer Science [cs]/Embedded SystemsUnified Modeling LanguageSoftware deploymentEmbedded systemComponent (UML)IP-XACT0202 electrical engineering electronic engineering information engineeringSystem integration[INFO.INFO-ES]Computer Science [cs]/Embedded Systems[ INFO.INFO-ES ] Computer Science [cs]/Embedded SystemsbusinesscomputerImplementationcomputer.programming_language
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Design and development of a fNIRS system prototype based on SiPM detectors

2014

Functional Near Infrared Spectroscopy (fNIRS) uses near infrared sources and detectors to measure changes in absorption due to neurovascular dynamics in response to brain activation. The use of Silicon Photomultipliers (SiPMs) in a fNIRS system has been estimated potentially able to increase the spatial resolution. Dedicated SiPM sensors have been designed and fabricated by using an optimized process. Electrical and optical characterizations are presented. The design and implementation of a portable fNIRS embedded system, hosting up to 64 IR-LED sources and 128 SiPM sensors, has been carried out. The system has been based on a scalable architecture whose elementary leaf is a flexible board …

business.industryComputer scienceDetectorNear-infrared spectroscopySettore ING-INF/02 - Campi ElettromagneticiNear Infrared SpectroscopySilicon PhotomultipliersReflectivitySettore ING-INF/01 - ElettronicaImaging phantomlaw.inventionOpticsSilicon photomultiplierlawOptoelectronicsSensitivity (control systems)businessEmbedded SystemsImage resolutionSilicon PhotomultiplierLight-emitting diode
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A Novel Approach for Accelerating Bitstream Relocation in Many-core Partially Reconfigurable Applications

2013

International audience; Partial Bitstream Relocation (PBR) has been introduced in recent years, as a means to overcome the limitations of the traditional Xilinx Partial Reconfiguration flow, particularly in terms of the limited module placement, a fact that can greatly reduce the memory footprint of applications which require multiple implementations of the same module... However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. This is particularly true in applications such as large scalable systems, which typically require multiple copies of the same module to accelerate a task, but in which the relocation time ov…

business.industryComputer scienceProcess (engineering)020208 electrical & electronic engineeringControl reconfigurationContext (language use)02 engineering and technology[INFO.INFO-ES] Computer Science [cs]/Embedded Systems020202 computer hardware & architectureEmbedded systemScalability0202 electrical engineering electronic engineering information engineeringMemory footprint[INFO.INFO-ES]Computer Science [cs]/Embedded Systems[ INFO.INFO-ES ] Computer Science [cs]/Embedded SystemsBitstreambusinessRelocationField-programmable gate array
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