Search results for "Embedded system"
showing 10 items of 291 documents
Distributed Symbolic Network Quality Assessment for Resource-constrained Devices
2021
After a Wireless Sensor Network (WSN) is deployed it is subject to significant variations of the quality of its radio links during its lifetime. Knowledge of the condition of the wireless links can be useful to optimize power consumption and increase the reliability of the network. However, resource-constrained nodes may not be able to spare the storage space for network monitoring code. Also, reprogramming deployed nodes can be costly or unfeasible. In this work, we show how an approach based on the exchange of symbolic executable code among nodes enables the assessment of the network status in terms of Packet Reception Rate (PRR) with no extra storage requirements on deployed networks. We…
Live demonstration: multiplexing AER asynchronous channels over LVDS Links with Flow-Control and Clock-Correction for Scalable Neuromorphic Systems
2017
Paper presented at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), held in Baltimore, MD, USA, on 28-31 May 2017.
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs f…
2017
Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation …
An embedded datalogger with a fast acquisition rate for in-vehicle testing and monitoring
2011
A very compact and high performance datalogger for automotive in-vehicle testing is here described. The small logger dimensions and the availability of a CAN interface allows to easily implement multiple and distributed acquisition schemes, very challenging with traditional instrumentation. High acquisition rate, up to 100 Ksps/ch, and low cost was obtained through a very accurate hardware and software design.
Exploring NoC Virtualization Alternatives in CMPs
2012
Chip Multiprocessor systems (CMPs) contain more and more cores in every new generation. However, applications for these systems do not scale at the same pace. Thus, in order to obtain a good utilization several applications will need to coexist in the system and in those cases virtualization of the CMP system will become mandatory. In this paper we analyze two virtualization strategies at NoC-level aiming to isolate the traffic generated by each application to reduce or even eliminate interferences among messages belonging to different applications. The first model handles most interferences among messages with a virtual-channels (VCs) implementation minimizing both execution time and netwo…
Adaptive Vehicle Mode Monitoring Using Embedded Devices with Accelerometers
2012
Monitoring of specific attributes such as vehicle speed and fuel consumption as well as cargo safety is an important problem for transport domain. This task is performed using specific multiagent monitoring systems. To ensure secure operation of such systems they should have autonomous and adaptive behaviour.
Implementation and Deployment Evaluation of the DMAMAC Protocol for Wireless Sensor Actuator Networks
2016
Abstract The increased application of wireless technologies including Wireless Sensor Actuator Networks (WSAN) in industry has given rise to a plethora of protocol designs. These designs target metrics ranging from energy efficiency to real-time constraints. Protocol design typically starts with a requirements specification, and continues with analytic and model-based simulation analysis. State-of- the-art network simulators provide extensive physical environment emulation, but still have limitations due to model abstractions. Deployment testing on actual hardware is therefore vital in order to validate implementability and usability in the real environment. The contribution of this article…
Analysis and Visualization of Product Memory Layout in IP-XACT
2017
Modern ASIC and FPGA based embedded products use model based design, in which both hardware and software are developed in parallel. Previously HW was completed first and the information handed over to SW team, typically in the form of register tables. The information was even manually copied to SW code, making any changes error-prone and laborious. IP-XACT is the most feasible standard to model HW also for the SW needs. The HW design connectivity and overall memory layout may change due to component instantiations, configurations and conditional operation states, which makes it difficult to create register tables even for documentation. Current register design tools fall short in serving th…
Knowledge-based verification of concatenative programming patterns inspired by natural language for resource-constrained embedded devices
2020
We propose a methodology to verify applications developed following programming patterns inspired by natural language that interact with physical environments and run on resource-constrained interconnected devices. Natural language patterns allow for the reduction of intermediate abstraction layers to map physical domain concepts into executable code avoiding the recourse to ontologies, which would need to be shared, kept up to date, and synchronized across a set of devices. Moreover, the computational paradigm we use for effective distributed execution of symbolic code on resource-constrained devices encourages the adoption of such patterns. The methodology is supported by a rule-based sys…
Energy Efficiency Evaluation of Dynamic Partial Reconfiguration in Field Programmable Gate Arrays: An Experimental Case Study
2018
Both computational performances and energy efficiency are required for the development of any mobile or embedded information processing system. The Internet of Things (IoT) is the latest evolution of these systems, paving the way for advancements in ubiquitous computing. In a context in which a large amount of data is often analyzed and processed, it is mandatory to adapt node logic and processing capabilities with respect to the available energy resources. This paper investigates under which conditions a partially reconfigurable hardware accelerator can provide energy saving in complex processing tasks. The paper also presents a useful analysis of how the dynamic partial reconfiguration te…