Search results for "Fault-tolerance"
showing 5 items of 5 documents
DC link voltage swinging and load current unbalance in fault tolerant VSI. overview and compensation strategies
2015
The topic of this paper is the discussion on the performance of a three-phase fault tolerant inverter with particular attention to the underrated aspect of current unbalances occurring due to the DC link voltage fluctuates after the inverter reconfiguration. Capacitor voltage unbalance affects not only the average output voltage of the inverter, but also its performance. In fact, the inverter performance depends on the fluctuating DC-link voltage components rather than on the average DC-link voltage. After a brief analysis of the voltage fluctuation phenomena resulting from fault tolerant configuration and their effect on load current unbalance, the Authors consider different compensating p…
Flexible Spare Core Placement in Torus Topology based NoCs and its validation on an FPGA
2021
In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized …
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems
2011
[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of usi…
DC/DC converter topologies for electrolyzers: State-of-the-art and remaining key issues.
2017
In recent years, the use of electrolyzers to produce cleanly and efficiently hydrogen from renewable energy sources (i.e. wind turbines, photovoltaic) has taken advantage of a growing interest from researchers and industrial. Similarly to fuel cells, DC/DC converters are needed to interface the DC bus with the electrolyzer. Usually, electrolyzers require a low DC voltage to produce hydrogen from water. For this reason, a DC/DC buck converter is generally used for this purpose. However, other DC/DC converter topologies can be used depending on the feature of the electrolyzer and electrical grid as well. The main purpose of this paper is to present the current state-of-the-art of DC/DC conver…
Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA
2021
Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant appli…