Search results for "Field-programmable gate array"
showing 5 items of 175 documents
A new ATLAS muon CSC readout system with system on chip technology on ATCA platform
2015
The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applicati…
A hardware skin-segmentation IP for vision based smart ADAS through an FPGA prototyping
2017
International audience; In this paper we presents a platform based design approach for fast HW/SW embedded smart Advanced Driver Assistant System (ADAS) design and prototyping. Then, we share our experience in designing and prototyping a HW/SW vision based smart embedded system as an ADAS that helps to increase the safety of car's drivers. We present a physical prototype of the vision ADAS based on a Zynq FPGA. The system detects the fatigue state of the driver by monitoring the eyes closure and generates a real-time alert. A new HW/SW codesign skin segmentation step to locate the eyes/face is proposed. Our presented new approach migrates the skin segmentation step from processing system (S…
A High speed data link optimization for digitalized transfer to processing FPGA
2021
State-of-the-art arrays of detectors, that require digital processing, may have a sizeable number of digitalized signal links. This is the case in several experimental nuclear physics instruments. Moreover, the data rate of the sampled signals, defined primary by the signal bandwidth of the individual detectors, may not exhaust the capabilities of a single FPGA transceiver input. The preprocessing is usually carried out in a modern FPGA with transceiver data rate capabilities over 10Gbps. Moreover, cost effective FPGA have a limited number of transceivers for given FPGA processing capabilities. The investigation of a cost-effective and efficient solution to the mismatch between both data ra…
FPGA-based Acceleration of Detecting Statistical Epistasis in GWAS
2014
Abstract Genotype-by-genotype interactions (epistasis) are believed to be a significant source of unexplained genetic variation causing complex chronic diseases but have been ignored in genome-wide association studies (GWAS) due to the computational burden of analysis. In this work we show how to benefit from FPGA technology for highly parallel creation of contingency tables in a systolic chain with a subsequent statistical test. We present the implementation for the FPGA-based hardware platform RIVYERA S6-LX150 containing 128 Xilinx Spartan6-LX150 FPGAs. For performance evaluation we compare against the method iLOCi[9]. iLOCi claims to outperform other available tools in terms of accuracy.…
A Novel Bio-Inspired Approach for High-Performance Management in Service-Oriented Networks
2021
Service-continuity in distributed computing can be enhanced by designing self-organized systems, with a non-fixed structure, able to modify their structure and organization, as well as adaptively react to internal and external environment changes. In this paper, an architecture exploiting a bio-inspired management approach, i.e., the functioning of cell metabolism, for specialized computing environments in Service-Oriented Networks (SONs) is proposed. Similar to the processes acting in metabolic networks, the nodes communicate to each other by means of stimulation or suppression chains giving rise to emergent behaviors to defend against foreign invaders, attacks, and malfunctioning. The mai…