Search results for "Finite-state machine"
showing 7 items of 97 documents
Bounded Computational Capacity Equilibrium
2010
We study repeated games played by players with bounded computational power, where, in contrast to Abreu and Rubisntein (1988), the memory is costly. We prove a folk theorem: the limit set of equilibrium payoffs in mixed strategies, as the cost of memory goes to 0, includes the set of feasible and individually rational payoffs. This result stands in sharp contrast to Abreu and Rubisntein (1988), who proved that when memory is free, the set of equilibrium payoffs in repeated games played by players with bounded computational power is a strict subset of the set of feasible and individually rational payoffs. Our result emphasizes the role of memory cost and of mixing when players have bounded c…
From UML Specification into FPGA Implementation
2014
In the paper a method of using the Unified Modeling Language for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine di- agrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams, expressed in XML language, to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Ar- rays). The UML specification is used to generate an eective program in Hardware Description Languages (HDLs), especially Verilog.
From UML State Machine Diagram into FPGA Implementation
2013
Abstract In the paper a method of using the Unified Modeling Language diagrams for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine diagrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Arrays). The UML specification is used to generate an effective program in Hardware Description Languages (HDLs), especially Verilog.
One size hardly fits all
2013
This paper casts recent accomplishments in the field of Wireless MAC programmability into the emerging Software Defined Networking perspective. We argue that an abstract (but formal) description of the MAC protocol logic in terms of extensible finite state machines appears a convenient and viable data-plane programming compromise for modeling and deploying realistic MAC protocol logics. Our approach is shown to comply with existing control frameworks, and entails the ability to dynamically change the MAC protocol operation based on context and scenario conditions; in essence, move from the traditional idea of "one-size-fits-all" MAC protocol stack to the innovative paradigm of opportunistic…
Varieties Generated by Certain Models of Reversible Finite Automata
2006
Reversible finite automata with halting states (RFA) were first considered by Ambainis and Freivalds to facilitate the research of Kondacs-Watrous quantum finite automata. In this paper we consider some of the algebraic properties of RFA, namely the varieties these automata generate. Consequently, we obtain a characterization of the boolean closure of the classes of languages recognized by these models.
CUDA-BLASTP: Accelerating BLASTP on CUDA-enabled graphics hardware
2011
Scanning protein sequence database is an often repeated task in computational biology and bioinformatics. However, scanning large protein databases, such as GenBank, with popular tools such as BLASTP requires long runtimes on sequential architectures. Due to the continuing rapid growth of sequence databases, there is a high demand to accelerate this task. In this paper, we demonstrate how GPUs, powered by the Compute Unified Device Architecture (CUDA), can be used as an efficient computational platform to accelerate the BLASTP algorithm. In order to exploit the GPU's capabilities for accelerating BLASTP, we have used a compressed deterministic finite state automaton for hit detection as wel…
A Self-Contained Biometric Sensor for Ubiquitous Authentication
2007
This paper describes a real-life behavior framework in simulation game based on Probabilistic State Machine (PSM) with Gaussian random distribution. According to the dynamic environment information, NPC can generate behavior planning autonomously associated with defined FSM. After planning process, we illuminate Gaussian probabilistic function for real-life action simulation in time and spatial domains. The expected value of distribution is estimated during behavior planning process and variance is determined by NPC personality in order to realize real life behavior simulation. We experiment the framework and Gaussian PSM on a restaurant simulation game. Furthermore we give some suggestions…