Search results for "Fpg"
showing 10 items of 131 documents
A reconfigurable platform for evaluating the performance of QoS networks
2010
Nowadays, high performance System and Local Area Networks (SAN/LAN) have to serve heterogeneous traffic consisting of information flows with different bandwidth and latency requirements. This makes it necessary to provide Quality of Service (QoS) and optimize the design of network components. In this paper we present a hardware tool designed to analyze the performance of QoS networks, under given traffic conditions and server models. In particular, a reprogrammable multimedia traffic Generator/Monitor platform has been built. This permits prototyping the communication system of a high speed LAN/SAN on a single FPGA device. Hence, it can be used at design to produce more efficient devices. T…
A Novel Architecture for Inter-FPGA Traffic Collision Management
2014
International audience; —with the increasing complexity of various communi-cations and applications, Network-On-Chip (NoC) is one of the most efficient communication structures. Multi-FPGA platforms are considered as the most appropriate experimental solutions to emulate a large size of MPSoCs (Multi-Processor System-on-Chip) based on a NoC. The deployment of the NoC into several FPGAs requires the use of inter-FPGA communication links. The number and performance of external links restrict the bandwidth of communication. Currently, the number of inter-FPGA signals is considered as a substantial problem in NoC implemented on Multi-FPGA architectures. In this paper, we propose the integration…
Non linear digital control improving transient response:design and test on a multiphase VRM
2010
FPGA Implementation of a Reconfigurable 802.11 Medium Access Control
THis work describes a full implementation of a reconfigurable IEEE 802.11 Medium Access Control (MAC) in FPGA using a System on Chip (SoC) architecture. The proposed implementation has been designed with a great structural flexibility, so to ease the protocol modification, and to support Quality of Service (QoS) function. Estensive tests has been carried out showing a full compliance to the 802.11 standard timing and algorithms.
Efficient FPGA Implementation of a Knowledge-Based Automatic Speech Classifier
2005
Speech recognition has become common in many application domains, from dictation systems for professional practices to vocal user interfaces for people with disabilities or hands-free system control. However, so far the performance of Automatic Speech Recognition (ASR) systems are comparable to Human Speech Recognition (HSR) only under very strict working conditions, and in general far lower. Incorporating acoustic-phonetic knowledge into ASR design has been proven a viable approach to rise ASR accuracy. Manner of articulation attributes such as vowel, stop, fricative, approximant, nasal, and silence are examples of such knowledge. Neural networks have already been used successfully as dete…
An Embedded Module for Iris Micro-Characteristics Extraction
2009
In this paper a new approach, based on iris micro-characteristics, has been used to make possible an embedded biometric extractor. This recognition approach is based on ophthalmologic studies that have proven the existence of different micro-characteristics as well as fingerprint minutiae. These micro-characteristics are permanent and immutable and they can be used to create strong and robust identification systems.Biometric recognition systems are critical components of our everyday lives. Since such electronic products evolve to software intensive systems, where software, becoming larger, more complex and prevalent, introduces many problems in the development phases. The development of em…
Graphic Coprocessors with Native Clifford Algebra Support
2009
ConformalALU: A Conformal Geometric Algebra Coprocessor for Medical Image Processing
2015
Medical imaging involves important computational geometric problems, such as image segmentation and analysis, shape approximation, three-dimensional (3D) modeling, and registration of volumetric data. In the last few years, Conformal Geometric Algebra (CGA), based on five-dimensional (5D) Clifford Algebra, is emerging as a new paradigm that offers simple and universal operators for the representation and solution of complex geometric problems. However, the widespread use of CGA has been so far hindered by its high dimensionality and computational complexity. This paper proposes a simplified formulation of the conformal geometric operations (reflections, rotations, translations, and uniform …
A Sliced Coprocessor for Native Clifford Algebra Operations
2007
Computer graphics applications require efficient tools to model geometric objects. The traditional approach based on compute-intensive matrix calculations is error-prone due to a lack of integration between geometric reasoning and matrix-based algorithms. Clifford algebra offers a solution to these issues since it permits specification of geometry at a coordinate-free level. The best way to exploit the symbolic computing power of geometric (Clifford) algebra is supporting its data types and operators directly in hardware. This paper outlines the architecture of S-CliffoSor (Sliced Clifford coprocessor), a parallelizable embedded coprocessor that executes native Clifford algebra operations. …
Design and implementation of an embedded coprocessor with native support for 5D, quadruple-based Clifford algebra
2013
Geometric or Clifford algebra (CA) is a powerful mathematical tool that offers a natural and intuitive way to model geometric facts in a number of research fields, such as robotics, machine vision, and computer graphics. Operating in higher dimensional spaces, its practical use is hindered, however, by a significant computational cost, only partially addressed by dedicated software libraries and hardware/software codesigns. For low-dimensional algebras, several dedicated hardware accelerators and coprocessing architectures have been already proposed in the literature. This paper introduces the architecture of CliffordALU5, an embedded coprocessing core conceived for native execution of up t…