Search results for "Hard"
showing 10 items of 2294 documents
Pain fingerprinting using multimodal sensing: pilot study
2021
Abstract Pain is a complex phenomenon, the experience of which varies widely across individuals. At worst, chronic pain can lead to anxiety and depression. Cost-effective strategies are urgently needed to improve the treatment of pain, and thus we propose a novel home-based pain measurement system for the longitudinal monitoring of pain experience and variation in different patients with chronic low back pain. The autonomous nervous system and audio-visual features are analyzed from heart rate signals, voice characteristics and facial expressions using a unique measurement protocol. Self-reporting is utilized for the follow-up of changes in pain intensity, induced by well-designed physical …
MultivariateApart: Generalized partial fractions
2021
We present a package to perform partial fraction decompositions of multivariate rational functions. The algorithm allows to systematically avoid spurious denominator factors and is capable of producing unique results also when being applied to terms of a sum separately. The package is designed to work in Mathematica, but also provides interfaces to the Form and Singular computer algebra systems.
On the Quantum and Classical Complexity of Solving Subtraction Games
2019
We study algorithms for solving Subtraction games, which are sometimes referred as one-heap Nim games.
Continuous Monitoring of Parasitic Elements in Boost Converter Circuit
2021
The given paper explains the necessity of condition monitoring for DC/DC boost converter circuit. Further, an analytical model of circuit parasitic estimation is presented based on measured quantities in the circuit. The implementation of continuous estimation of circuit parasitic elements is analytically explained and verified by simulations and experimental results. Obtained results are acceptable for condition monitoring.
Multiprocessor SoC Implementation of Neural Network Training on FPGA
2008
Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for gr…
A Communication-Aware Topological Mapping Technique for NoCs
2008
Networks---on---Chip (NoCs) have been proposed as a promising solution to the complex on-chip communication problems derived from the increasing number of processor cores. The design of NoCs involves several key issues, being the topological mapping (the mapping of the Intellectual Properties (IPs) to network nodes) one of them. Several proposals have been focused on topological mapping last years, but they require the experimental validation of each mapping considered. In this paper, we propose a communication-aware topological mapping technique for NoCs. This technique is based on the experimental correlation of the network model with the actual network performance, thus avoiding the need…
Analysis of Interconnected Earthing Systems of MV/LV Substations in Urban Areas
2008
The paper proposes a study of the fault current distribution in an extended interconnection of earthing systems, belonging to secondary substations, during a single-line-to-earth fault. By applying the analysis methodology defined by the same authors in some previous works, the paper shows how the value of some important geometrical and electrical parameters of a MV network can influence the value of the earth current at the fault location.
Domain-Knowledge Optimized Simulated Annealing for Network-on-Chip Application Mapping
2013
Network-on-Chip architectures are scalable on-chip interconnection networks. They replace the inefficient shared buses and are suitable for multicore and manycore systems. This paper presents an Optimized Simulated Annealing (OSA) algorithm for the Network-on-Chip application mapping problem. With OSA, the cores are implicitly and dynamically clustered using knowledge about communication demands. We show that OSA is a more feasible Simulated Annealing approach to NoC application mapping by comparing it with a general Simulated Annealing algorithm and a Branch and Bound algorithm, too. Using real applications we show that OSA is significantly faster than a general Simulated Annealing, withou…
Upport vector machines for nonlinear kernel ARMA system identification.
2006
Nonlinear system identification based on support vector machines (SVM) has been usually addressed by means of the standard SVM regression (SVR), which can be seen as an implicit nonlinear autoregressive and moving average (ARMA) model in some reproducing kernel Hilbert space (RKHS). The proposal of this letter is twofold. First, the explicit consideration of an ARMA model in an RKHS (SVM-ARMA 2k) is proposed. We show that stating the ARMA equations in an RKHS leads to solving the regularized normal equations in that RKHS, in terms of the autocorrelation and cross correlation of the (nonlinearly) transformed input and output discrete time processes. Second, a general class of SVM-based syste…
Automatic construction of test sets: Theoretical approach
2005
We consider the problem of automatic construction of complete test set (CTS) from program text. The completeness criterion adopted is C1, i.e., it is necessary to execute all feasible branches of program at least once on the tests of CTS. A simple programming language is introduced with the property that the values used in conditional statements are not arithmetically deformed. For this language the CTS problem is proved to be algorithmically solvable and CTS construction algorithm is obtained. Some generalizations of this language containing counters, stacks or arrays are considered where the CTS problem remains solvable. In conclusion the applications of the obtained results to CTS constr…