Search results for "Hard"

showing 10 items of 2294 documents

A readout unit for high rate applications

2002

The LHCb readout unit (RU) is a custom entry stage to the readout network of a data-acquisition or trigger system. It performs subevent building from multiple link inputs toward a readout network via a PCI network interface or alternatively toward a high-speed link, via an S-link interface. Incoming event fragments are derandomized, buffered and assembled into single subevents. This process is based on a low-overhead framing convention and matching of equal event numbers. Programmable logic is used both in the input and output stages of the RU module, which may be configured either as a data-link multiplexer or as entry stage to a readout or trigger network. All FPGAs are interconnected via…

Hardware architectureNuclear and High Energy Physicsbusiness.industryComputer scienceInitializationNetwork interfaceMultiplexingMultiplexerlaw.inventionProgrammable logic deviceMicroprocessorNuclear Energy and EngineeringlawElectronic engineeringElectrical and Electronic EngineeringbusinessField-programmable gate arrayComputer hardwareIEEE Transactions on Nuclear Science
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Communication Interface Generation For HW/SW Architecture In The STARSoC Environment

2006

Mapping the application functionality to software and hardware requires automated methods to specify, generate and optimize the hardware, software, and the interface architectures between them. In this paper, we present a methodology flow to hardware-software communication synthesis for system-on-a-chip (SoC) design through STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-on-a-Chip) tool for rapid prototyping. Our concept consists of a set of hardware and software processes, described in C-code, communicates through the streams channels. This methodology consists in analyzing dependences of data between processes and synthesis a custom architecture to interface it. Firstly, we…

Hardware architectureResource-oriented architectureComputer sciencebusiness.industryInterface (computing)Software prototypingcomputer.software_genreSoftware frameworkComputer architectureEmbedded systemComponent-based software engineeringReference architecturebusinesscomputerFPGA prototype2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)
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AMCAS: Advanced Methods for the Co-Design of Complex Adaptive Systems

2006

Abstract This work proposes a new approximation to design and program Complex Adaptive Systems (CAS), these systems comprise neural network, intelligent agents, genetic algorithms, support vector machines and artificial intelligence systems in general. Due to the complexity of such systems, it is necessary to build a design environment able to ease the design work, allowing reusability and easy migration to hardware and/or software. Ptolemy II is used as the base system to simulate and evaluate the designs with different Models of Computation so that an optimum decision about the hardware or software implementation platform can be taken.

Hardware architectureSystem of systemsComputer sciencebusiness.industryModel of computationDistributed computingcomputer.software_genreIntelligent agentSoftwareComputer engineeringSystems development life cycleSystems designHardware compatibility listbusinesscomputerReusability
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Pathological voice analysis via digital signal processing

2015

The interest in pathological voice analysis for specific neurological diseases is growing up aiming to offer more Health-care tele monitoring services since new high performing electronic devices are available for the end-user. In this article we show some parameters that can be digitally extracted and analyzed from pathological voices, in order to find a distinctive sign of the Parkinson disease. As a result, we will show a parameter that gives some information about the Parkinson disease characterization, particularly for male patients. We will also discuss about the needed computational cost related to parameters extraction and elaboration, aiming to target a possible tough yet portable …

Hardware architecturebusiness.industryComputer scienceTele monitoringPathological voiceMutual informationSettore ING-INF/01 - ElettronicaIndustrial and Manufacturing EngineeringVoice analysisMutual informationParkinson diseaseHuman–computer interactionMale patientWavelet transformbusinessDigital signal processing
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Informática I (Fundamentos de la informática para los nuevos estudiantes de Grado) (2009/2010)

2009

Esta asignatura cubre los fundamentos de las Tecnologías de la Información y la Comunicación (TIC), la arquitectura de los computadores y los conceptos generales de los algoritmos. Además, introduce los sistemas operativos y las redes de comunicación, junto con una formación avanzada con paquetes de ofimática.

HardwareProgramarioIngenieria y ArquitecturaTecnologías de la Información y la ComunicaciónUNESCO::MATEMÁTICAS::Ciencia de los ordenadoresTecnologías de la información y la comunicacióOCWSoftware
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Visualization2.mov

2019

movie representing the subtraction hologram derived from Eq. 3 in the paper

Hardware_ARITHMETICANDLOGICSTRUCTURESComputingMilieux_MISCELLANEOUSComputingMethodologies_COMPUTERGRAPHICS
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Visualization2.mov

2019

movie representing the subtraction hologram derived from Eq. 3 in the paper

Hardware_ARITHMETICANDLOGICSTRUCTURESComputingMilieux_MISCELLANEOUSComputingMethodologies_COMPUTERGRAPHICS
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Optimization of capacitor banks in the Skagerak networks transmission grid

2013

Masteroppgave i fornybar energi ENE500 2013 – Universitetet i Agder, Grimstad Capacitor banks have been widely used in electric power networks. This master thesis presents a study of introducing new capacitor banks into a transmission network. The network comprises two areas at Telemark and Vestfold with voltages levels of 55kV, 66kV and 132kV, owned by Skagerak Nett AS. Capacitor banks improve the electric network in five ways: power factor correction, increased capacity, reduction of losses, voltage support and reactive power support. International standards and regulations regarding capacitor banks usage, as well as technological related considerations, have been explained. Network impro…

Hardware_GENERAL
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European Banking Union and bank risk disclosure: the effects of the Single Supervisory Mechanism

2022

AbstractThis paper provides evidence on the impact of European Banking Union (BU) and the associated Single Supervisory Mechanism (SSM) on the risk disclosure practices of European banks. The onset of BU and the associated rules are considered as an exogenous shock that provides the setting for a natural experiment to analyze the effects of the new supervisory arrangements on bank risk disclosure practices. A Difference-in-Differences approach is adopted, building evidence from the disclosure practices of systemically important banks supervised by the European Central Bank (ECB) and other banks supervised by national regulators over the period 2012–2017. The main findings are that bank risk…

Hardware_MEMORYSTRUCTURES050208 financeNatural experimentRisk disclosureSettore SECS-P/11 - Economia Degli Intermediari Finanziari05 social sciencesEuropean central bankPrincipal–agent problemFinancial systemBanking unionGeneral Business Management and AccountingPrincipal-agent problemSingle supervisory mechanismCorporate financeBank riskBanksAccounting0502 economics and businessBanking unionBusinessInformation flow (information theory)050207 economicsFinanceReview of Quantitative Finance and Accounting
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FADaC

2019

Solid state drives (SSDs) implement a log-structured write pattern, where obsolete data remains stored on flash pages until the flash translation layer (FTL) erases them. erase() operations, however, cannot erase a single page, but target entire flash blocks. Since these victim blocks typically store a mix of valid and obsolete pages, FTLs have to copy the valid data to a new block before issuing an erase() operation. This process therefore increases the latencies of concurrent I/Os and reduces the lifetime of flash memory. Data classification schemes identify data pages with similar update frequencies and group them together. FTLs can use this grouping to design garbage collection strategi…

Hardware_MEMORYSTRUCTURESComputer science0202 electrical engineering electronic engineering information engineeringOperating system020206 networking & telecommunications02 engineering and technologycomputer.software_genrecomputerClassifier (UML)Flash memoryFlash file system020202 computer hardware & architectureGarbage collectionProceedings of the 12th ACM International Conference on Systems and Storage
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