Search results for "Hardware description language"
showing 5 items of 15 documents
From UML State Machine Diagram into FPGA Implementation
2013
Abstract In the paper a method of using the Unified Modeling Language diagrams for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine diagrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Arrays). The UML specification is used to generate an effective program in Hardware Description Languages (HDLs), especially Verilog.
AER Filtering Using GLIDER: VHDL Cellular Automata Description
2008
Cellular Automata (CA) is a bio-inspired processing model for problem solving, initially proposed by Von Neumann. This approach modularizes the processing by dividing the solution into synchronous cells that change their states at the same time in order to get the solution. The communication between them is crucial to achieve the correct solution. On the other hand, the Address-Event-Representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI chips. These neuro-inspired implementations have been used to design sensor chips (retina, cochleas), processing chips (convolutions, filters) and learning chips, which makes it possible to develop co…
Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: a XILINX EDK case study
2012
International audience; In this paper we present framework for the deployment of hardware IPs at high-levels of abstraction. It is based in a model- driven approach that aims at the automatic generation of Dynamic Partial Reconfiguration designs created in Xilinx Platform Studio (XPS). Contrary to previous approaches, we make use of the IP-XACT standard to facilitate the deployment of hardware IPs, their parameterization and subsequent integration. We propose an extension to the MARTE profile for IP deployment, and we introduce the necessary model transformations to obtain a high- level representation from an IP-XACT component library. These models are then used to create a platform in MART…
AES/FPGA Encryption Module Integration for Satellite Remote Sensing Systems: LST-SW case
2020
Satellite remote sensing embedded systems need to be secure to protect data transmission between satellites and the ground station for any threat can affects the hardware of satellite and interception of data, in addition to unauthorized access to satellite system. This research proposes an approach for a secure integration of FPGA Encryption module based on the iterative looping architecture for remote sensing algorithm and especially for the LST-SW algorithm. The target hardware used in this paper is Virtex-5 XC5VLX50T FPGA from Xilinx. Hardware Description Language was used to design the complete system. The analysis of the proposed designed shows that this implementation can achieved a …
An efficient hardware implementation of Diamond Search motion estimation using CAL dataflow language
2011
Motion estimation represents a key module in video compression. The Reconfigurable Video Coding context (RVC) requires proposing a flexible solution for motion estimation. The motion estimation performance should be modified to fit with the user or the environment's constraints. Depending on the required performances fixed by the application, a full search is sometimes not suitable, hence, alternative fast/reduced solutions should be considered. In this paper, an efficient Diamond Search motion estimation, described in RVC-CAL actor language, is introduced. Starting from a high level description based CAL language, an automatic translation of the proposed CAL module to HDL is performed. Thi…