Search results for "Large"
showing 10 items of 2197 documents
Fault Emulation for Dependability Evaluation of VLSI Systems
2008
Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently pro posed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the cost of fixing any error due to their applicability in the first steps of the development cycle. However, only a reduced set of fault models, mainly stuck-at and bit-flip, have been considered in fault emulation approaches. This paper describes the procedures to inje…
A VLSI for deskewing and fault tolerance in LVDS links
2005
The device presented at this work is a switch implemented in a 0.35 mum CMOS process for compensating the skew which affects parallel data signal transmissions and for providing fault tolerance in large scale scalable systems, for instance used in trigger farms for high energy physics experiments. The SWIFT chip (SWItch for Fault Tolerance) is part of a cluster built around commercially components which has been inspired by the LHCb experiment. The skew is extremely important because it directly affects the sample window available to the receiver logic and either forces to use quality and expensive cables in order to minimize its effects or reduces the maximum signal transmission range or d…
CIPRNG: A VLSI Family of Chaotic Iterations Post-Processings for $\mathbb {F}_{2}$ -Linear Pseudorandom Number Generation Based on Zynq MPSoC
2018
Hardware pseudorandom number generators are continuously improved to satisfy both physical and ubiquitous computing security system challenges. The main contribution of this paper is to propose two post-processing modules in hardware, to improve the randomness of linear PRNGs while succeeding in passing the TestU01 statistical battery of tests. They are based on chaotic iterations and are denoted by CIPRNG-MC and CIPRNG-XOR. They have various interesting properties, encompassing the ability to improve the statistical profile of the generators on which they iterate. Such post-processing have been implemented on FPGA and ASIC without inferring any blocs (RAM or DSP). A comparison in terms of …
Visual spike-based convolution processing with a Cellular Automata architecture
2010
this paper presents a first approach for implementations which fuse the Address-Event-Representation (AER) processing with the Cellular Automata using FPGA and AER-tools. This new strategy applies spike-based convolution filters inspired by Cellular Automata for AER vision processing. Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. AER is a neuromorphic communication protocol for transferring asynchronous events between VLSI spike-based chips. These neuro-inspired implementations allow developing complex, multilayer, multichip neuromorphic systems and have been used to design sensor chips, such as retinas an…
Optimized FPGA-implementation of quadrature DDS
2003
This paper presents the optimized implementation of high performance quadrature direct digital synthesizers (DDS). Although VLSI designs and optimizations have already been discussed in the literature they may not be successfully translated into an FPGA-based technology. This work examines each phase-to-amplitude mapping technique, such as ROM compression and partitioning techniques and the CORDIC algorithm, and it proposes the most suitable structure for Virtex FPGAs in order to obtain the most efficient implementation in terms of area and throughput.
AER Filtering Using GLIDER: VHDL Cellular Automata Description
2008
Cellular Automata (CA) is a bio-inspired processing model for problem solving, initially proposed by Von Neumann. This approach modularizes the processing by dividing the solution into synchronous cells that change their states at the same time in order to get the solution. The communication between them is crucial to achieve the correct solution. On the other hand, the Address-Event-Representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI chips. These neuro-inspired implementations have been used to design sensor chips (retina, cochleas), processing chips (convolutions, filters) and learning chips, which makes it possible to develop co…
Programmable VLSI cubic-like function implementation
2006
An analogue VLSI implementation of a cubic-like function is presented, whose design is focused to reduce the circuit complexity. Simulations show that the V–I characteristic of the circuit resembles a cubic function, which can be easily adjusted by changing the bias parameters.
Global Trigger Technological Demonstrator for ATLAS Phase-II upgrade
2020
ATLAS detector at the LHC will undergo a major Phase-II upgrade for the High Luminosity LHC. The upgrade affects all major ATLAS systems, including the Trigger and Data Acquisition systems. As part of the Level-0 Trigger System, the Global Trigger uses full-granularity calorimeter cells to perform algorithms, refines the trigger objects and applies topological requirements. The Global Trigger uses a Global Common Module as the building block of its design. To achieve a high input and output bandwidth and substantial processing power, the Global Common Module will host the most advanced FPGAs and optical modules. In order to evaluate the new generation of optical modules and FPGAs running at…
Combination of Searches for Invisible Higgs Boson Decays with the ATLAS Experiment
2019
Dark matter particles, if sufficiently light, may be produced in decays of the Higgs boson. This Letter presents a statistical combination of searches for H → invisible decays where H is produced according to the standard model via vector boson fusion, Z(ℓℓ)H, and W/Z(had)H, all performed with the ATLAS detector using 36.1 fb⁻¹ of pp collisions at a center-of-mass energy of √s = 13 TeV at the LHC. In combination with the results at √s = 7 and 8 TeV, an exclusion limit on the H → invisible branching ratio of 0.26(0.17-0.05+0.07) at 95% confidence level is observed (expected).
Structure of longitudinal chromomagnetic fields in high energy collisions
2014
We compute expectation values of spatial Wilson loops in the forward light cone of high-energy collisions. We consider ensembles of gauge field configurations generated from a classical Gaussian effective action as well as solutions of high-energy renormalization group evolution with fixed and running coupling. The initial fields correspond to a color field condensate exhibiting domain-like structure over distance scales of order the saturation scale. At later times universal scaling emerges at large distances for all ensembles, with a nontrivial critical exponent. Finally, we compare the results for the Wilson loop to the two-point correlator of magnetic fields.