Search results for "MPSoC"
showing 7 items of 7 documents
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology
2010
Nowadays, system designers have adopted Networks-on-Chip as communication infrastructure of general-purpose tile-based Multi-Processor System-on-Chip (MPSoC). Such decision implies that a certain topology has to be selected to efficiently interconnect many cores on the chip. To ease such a choice, the networking literature offers a plethora of works about topology analysis and characterization for the off-chip domain. However, theoretical parameters and many intuitive assumptions of such off-chip networks do not necessarily hold when a topology is laid out on a 2D silicon surface. This is due to the distinctive features of silicon technology design pitfalls. This work is a first milestone t…
TLMCO-simulation for an open source MPSOC platform under STARSoC environment
2008
In the last decade, the embedded systems become more and more complex. This complexity is due to the fact that these systems contain more heterogeneous hardware and software components (CPUpsilas, DSP, IP, etc.). Such systems called multiprocessor-on-chip (MPSoC) require new design approaches in order to satisfy several constraints, verification time, cost and time to market.
Rapid prototyping platform for stream-oriented reconfigurable computing applications
2010
In this paper we present a methodology and tool for rapid prototyping of real time image processing applications. We describe our design flow of multiprocessor system on chip (MPSoC) architectures based on hardware/software components. This methodology provides automated methods to specify, generate the hardware, software, and the architectural interfaces between them. Our methodology starts from system level specification of the application with parallel processes described in C-code. The processes communicate through an abstract channel called streams. We describe also the solution that we proposed to synthesize a custom bus architecture for the reconfigurable computing applications, whic…
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems
2011
[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of usi…
Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platform
2007
The communication synthesis is the main problematic in the multiprocessor system-on-chip (MPSoC). To resolve this problem, several methodologies can be used. These methodologies require automated methods to specify, generate and optimize the hardware, software, and the architectural interfaces between them. In this paper, we present a methodology flow for hardware-software communication synthesis for multiprocessor system-on-chip platform which are dedicated to streaming applications. Our methodology consists of high level architecture communication synthesis from functional description of the MPSoC design. The solution that we propose consists in synthesizing a custom bus architecture for …
CIPRNG: A VLSI Family of Chaotic Iterations Post-Processings for $\mathbb {F}_{2}$ -Linear Pseudorandom Number Generation Based on Zynq MPSoC
2018
Hardware pseudorandom number generators are continuously improved to satisfy both physical and ubiquitous computing security system challenges. The main contribution of this paper is to propose two post-processing modules in hardware, to improve the randomness of linear PRNGs while succeeding in passing the TestU01 statistical battery of tests. They are based on chaotic iterations and are denoted by CIPRNG-MC and CIPRNG-XOR. They have various interesting properties, encompassing the ability to improve the statistical profile of the generators on which they iterate. Such post-processing have been implemented on FPGA and ASIC without inferring any blocs (RAM or DSP). A comparison in terms of …
Co-simulation platform based on systemc for multiprocessor system on chip architecture exploration
2007
Currently multiprocessor embedded systems are the principal vectors of semiconductor industry. Modelling, validating and analyzing a system performances impose the evolution of the traditional simulation techniques. In this paper we define the methodology we used in constructing the STARSoC co-simulation environment. This platform aims to explore at higher levels of abstractions a multiprocessors system on chip architectures. The platform reference design contains several OpenRISC 1200 Instruction Set Simulators (ISSs) wrapped under SystemC, and some basic peripherals within the SystemC simulation framework. Our purpose is to develop a complete design space exploration tool. In order to ass…