Search results for "ON-CHIP"
showing 10 items of 20 documents
0.48Tb/s (12x40Gb/s) WDM transmission and high-quality thermo-optic switching in dielectric loaded plasmonics
2012
We demonstrate Wavelength Division Multiplexed (WDM)-enabled transmission of 480Gb/s aggregate data traffic (12x40Gb/s) as well as high-quality 1x2 thermo-optic tuning in Dielectric-Loaded Surface Plasmon Polariton Waveguides (DLSPPWs). The WDM transmission characteristics have been verified through BER measurements by exploiting the heterointegration of a 60 mu m-long straight DLSPPW on a Silicon-on-Insulator waveguide platform, showing error-free performance for six out of the twelve channels. High-quality thermo-optic tuning has been achieved by utilizing Cycloaliphatic-Acrylate-Polymer as an efficient thermo-optic polymer loading employed in a dual-resonator DLSPPW switching structure, …
Design of large scale sensors in 180 nm CMOS process modified for radiation tolerance
2019
International audience; The last couple of years have seen the development of Depleted Monolithic Active Pixel Sensors (DMAPS) fabricated with a process modification to increase the radiation tolerance. Two large scale prototypes, Monopix with a column drain synchronous readout, and MALTA with a novel asynchronous architecture, have been fully tested and characterized both in the laboratory and in test beams. This showed that certain aspects have to be improved such as charge collection after irradiation and the output data rate. Some improvements resulting from extensive TCAD simulations were verified on a small test chip, Mini-MALTA. A detailed cluster analysis, using data from laboratory…
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems
2011
[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of usi…
Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA
2021
Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant appli…
Flexible Spare Core Placement in Torus Topology based NoCs and its validation on an FPGA
2021
In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized …
Analog Photonic Fractional Signal Processing
2018
In this work, we provide an up to date overview on the subject of photonic fractional signal processing, including both, in-fiber and waveguide on-chip technology. Thus, we discuss in detail fractional differentiation, fractional integration, fractional Hilbert transforms, and finally, fractional Fourier transforms. In each case, the underlying mathematical principles are explained for each operation, together with a short historical discussion in the context of classical optics. After that, the different proposals to perform these operations photonically on the complex field envelope of a given light pulse are presented, divided according to its working principle. Finally, current applicat…
NoC based virtualized FPGA as cloud Services
2016
International audience; Web-based applications are increasingly demanding many computationally intensive services. On the other hand, FPGA-based hardware accelerators(HwAcc) provide good performance in accelerating computationally intensive applications. In addition, some FPGAs support a dynamic partial reconfig-uration (DPR) techniques to virtualize and share the FPGA underlying hardware resources in time multiplexing during run-time to save resource and power consumption. Integrating FPGA in a cloud environment is an indispensable way to improve efficiency and provide acceleration services to demanding users. More importantly, in recent years it was proved that FPGA resources deployed in …
Development of a microfluidic design for an automatic lab-on-chip operation
2016
Simple and easy to use are the keys for developing lab-on-chip technology. Here, a new microfluidic circuit has been designed for an automatic lab-on-chip operation (ALOCO) device. This chip used capillary forces for controlled and precise manipulation of liquids, which were loaded in sequence from different flowing directions towards the analysis area. Using the ALOCO design, a non-expert user is able to operate the chip by pipetting liquids into suitable inlet reservoirs. To test this design, microfluidic devices were fabricated using the programmable proximity aperture lithography technique. The operation of the ALOCO chip was characterized from the flow of red-, blue- and un-dyed deioni…
NF-ĸB as node for signal amplification during weaning.
2011
Post-lactational involution has been reported to share common features with breast tumor development. A deep characterization of the signaling triggered after weaning would help to unveil the complex relationship between involution and breast cancer. NF-κB, a crucial factor in the involuting gland, might be an important regulatory node for signal amplification after weaning; however there is limited information about the identity of NF-κB-target genes and the molecular mechanisms leading to the selection of genes involved in a particular biological process. We identified 4532 target genes in mammary gland at 48h weaning, by genome-wide analysis of regions bound by RelA(p65)-NF-κB in vivo. I…
Comprehensive analysis of interacting proteins and genome-wide location studies of the Sas3-dependent NuA3 histone acetyltransferase complex
2014
Highlights • We characterise Sas3p and Gcn5p active HAT complexes in WT and deleted TAP-strains. • We confirm that Pdp3p interacts with NuA3, histones and chromatin regulators. • Pdp3p MS-analysis reveals its phosphorylation, ubiquitination and methylation. • Sas3p can substitute Gcn5p in acetylation of histone H3K14 but not of H3K9. • Genome-wide profiling of Sas3p supports its involvement in transcriptional elongation.