Search results for "RDW"

Enhanced sampling in simulations of dense systems

2002

In the simulations of a variety of systems we encounter the problem of large relaxation times due to the dense packing of the systems constituents. We propose an algorithm to overcome this slowing down by temporarily allowing the constituents of a 3d systems to escape into a 4th space coordinate. The idea will be exemplified for the problem of a homopolymer collapse.

SYSTOLIC GENERATION OF k-ARY TREES

1999

The only parallel generating algorithms for k-ary trees are those of Akl and Stojmenović in 1996 and of Vajnovszki and Phillips in 1997. In the first of them, trees are represented by an inversion table and the processor model is a linear aray multicomputer. In the second, trees are represented by bitstrings and the algorithm executes on a shared memory multiprocessor. In this paper we give a parallel generating algorithm for k-ary trees represented by generalized P–sequences for execution on a linear array multicomputer.

Editorial

2002

Status indicators in software engineering group projects

2023

A segment of studies on group structure and performance in software engineering (SE) project-based learning (PjBL) have focused on roles, including studies that use Belbin team roles and studies that address problematic roles such as social loafing. The present study focuses on the status, which is basically missing in SE PjBL studies, although relating to roles. The study investigates the aspects that students identified as indicators of rising or declining status in their project groups. The status theory was utilized as the framework that motivated the research and on which the results were reflected. An inductive qualitative content analysis was applied to learning reports in which stud…

Implementation of a new adaptive algorithm using fuzzy cost function and robust to impulsive noise

2012

Adaptive filters are used in a wide range of applications such as noise cancellation, system identification, and prediction. One of the main problems for theses filters is the impulsive noise as it generates algorithm unstability. This work shows the development, simulation and hardware implementation of a new algorithm robust to impulsive noise. Hardware implementation becomes essential in many cases where a real time execution, reduced size, or low power system is needed. An efficient hardware architecture is proposed and different optimizations for size and speed are developed: no need for control state machine, reduced computation requirements due to simplifications, etc. Furthermore, t…

From Arithmetic to Logic based AI: A Comparative Analysis of Neural Networks and Tsetlin Machine

2020

Neural networks constitute a well-established design method for current and future generations of artificial intelligence. They depends on regressed arithmetic between perceptrons organized in multiple layers to derive a set of weights that can be used for classification or prediction. Over the past few decades, significant progress has been made in low-complexity designs enabled by powerful hardware/software ecosystems. Built on the foundations of finite-state automata and game theory, Tsetlin Machine is increasingly gaining momentum as an emerging artificial intelligence design method. It is fundamentally based on propositional logic based formulation using booleanized input features. Rec…

New developments in simulation-based harbour crane training

2011

This paper presents the efforts that have been made during the development of a set of harbour training simulators to improve their quality. The paper focuses on two main research lines: the improvement of complex physical systems involved in the simulation and the analysis of hardware architecture solutions. Cable-based hoist systems and bulk materials are systems present in different harbour equipment and are usually simulated with poor quality due to their complexity. In this paper physics-based models for the interactive simulation of these systems are proposed and applied to real cases. Also, different hardware simulator architectures are analysed and different approaches are proposed …

A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

2019

New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in la…

A Specialized Architecture for Color Image Edge Detection Based on Clifford Algebra

2013

Edge detection of color images is usually performed by applying the traditional techniques for gray-scale images to the three color channels separately. However, human visual perception does not differentiate colors and processes the image as a whole. Recently, new methods have been proposed that treat RGB color triples as vectors and color images as vector fields. In these approaches, edge detection is obtained extending the classical pattern matching and convolution techniques to vector fields. This paper proposes a hardware implementation of an edge detection method for color images that exploits the definition of geometric product of vectors given in the Clifford algebra framework to ex…

A readout unit for high rate applications

2002

The LHCb readout unit (RU) is a custom entry stage to the readout network of a data-acquisition or trigger system. It performs subevent building from multiple link inputs toward a readout network via a PCI network interface or alternatively toward a high-speed link, via an S-link interface. Incoming event fragments are derandomized, buffered and assembled into single subevents. This process is based on a low-overhead framing convention and matching of equal event numbers. Programmable logic is used both in the input and output stages of the RU module, which may be configured either as a data-link multiplexer or as entry stage to a readout or trigger network. All FPGAs are interconnected via…