Search results for "Software"

showing 10 items of 7396 documents

CUDA-enabled Sparse Matrix–Vector Multiplication on GPUs using atomic operations

2013

We propose the Sliced Coordinate Format (SCOO) for Sparse Matrix-Vector Multiplication on GPUs.An associated CUDA implementation which takes advantage of atomic operations is presented.We propose partitioning methods to transform a given sparse matrix into SCOO format.An efficient Dual-GPU implementation which overlaps computation and communication is described.Extensive performance comparisons of SCOO compared to other formats on GPUs and CPUs are provided. Existing formats for Sparse Matrix-Vector Multiplication (SpMV) on the GPU are outperforming their corresponding implementations on multi-core CPUs. In this paper, we present a new format called Sliced COO (SCOO) and an efficient CUDA i…

SpeedupComputer Networks and CommunicationsComputer scienceSparse matrix-vector multiplicationParallel computingComputer Graphics and Computer-Aided DesignTheoretical Computer ScienceMatrix (mathematics)CUDAArtificial IntelligenceHardware and ArchitectureBenchmark (computing)MultiplicationGeneral-purpose computing on graphics processing unitsSoftwareSparse matrixParallel Computing
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Finding near-perfect parameters for hardware and code optimizations with automatic multi-objective design space explorations

2012

Summary In the design process of computer systems or processor architectures, typically many different parameters are exposed to configure, tune, and optimize every component of a system. For evaluations and before production, it is desirable to know the best setting for all parameters. Processing speed is no longer the only objective that needs to be optimized; power consumption, area, and so on have become very important. Thus, the best configurations have to be found in respect to multiple objectives. In this article, we use a multi-objective design space exploration tool called Framework for Automatic Design Space Exploration (FADSE) to automatically find near-optimal configurations in …

SpeedupComputer Networks and CommunicationsDesign space explorationComputer sciencebusiness.industryParallel computingProgram optimizationMulti-objective optimizationComputer Science ApplicationsTheoretical Computer ScienceMicroarchitectureComputational Theory and MathematicsScalabilityCode (cryptography)Engineering design processbusinessSoftwareComputer hardwareConcurrency and Computation: Practice and Experience
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CliffoSor: A Parallel Embedded Architecture for Geometric Algebra and Computer Graphics

2006

Geometric object representation and their transformations are the two key aspects in computer graphics applications. Traditionally, compute-intensive matrix calculations are involved to model and render 3D scenery. Geometric algebra (a.k.a. Clifford algebra) is gaining growing attention for its natural way to model geometric facts coupled with its being a powerful analytical tool for symbolic calculations. In this paper, the architecture of CliffoSor (Clifford Processor) is introduced. ClifforSor is an embedded parallel coprocessing core that offers direct hardware support to Clifford algebra operators. A prototype implementation on an FPGA board is detailed. Initial test results show more …

SpeedupComputer scienceClifford algebraSolid modelingParallel computingComputational geometryApplication softwarecomputer.software_genreComputational scienceComputer graphicsGeometric algebraComputingMethodologies_SYMBOLICANDALGEBRAICMANIPULATIONRepresentation (mathematics)computer
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Improved SOM Learning using Simulated Annealing

2007

Self-Organizing Map (SOM) algorithm has been extensively used for analysis and classification problems. For this kind of problems, datasets become more and more large and it is necessary to speed up the SOM learning. In this paper we present an application of the Simulated Annealing (SA) procedure to the SOM learning algorithm. The goal of the algorithm is to obtain fast learning and better performance in terms of matching of input data and regularity of the obtained map. An advantage of the proposed technique is that it preserves the simplicity of the basic algorithm. Several tests, carried out on different large datasets, demonstrate the effectiveness of the proposed algorithm in comparis…

SpeedupMatching (graph theory)Wake-sleep algorithmComputer sciencebusiness.industryPattern recognitioncomputer.software_genreAdaptive simulated annealingGeneralization errorComputingMethodologies_PATTERNRECOGNITIONSimulated annealingSOM simulated Annealing TrainingData miningArtificial intelligencebusinesscomputer
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Reconfigurable Accelerator for the Word-Matching Stage of BLASTN

2013

BLAST is one of the most popular sequence analysis tools used by molecular biologists. It is designed to efficiently find similar regions between two sequences that have biological significance. However, because the size of genomic databases is growing rapidly, the computation time of BLAST, when performing a complete genomic database search, is continuously increasing. Thus, there is a clear need to accelerate this process. In this paper, we present a new approach for genomic sequence database scanning utilizing reconfigurable field programmable gate array (FPGA)-based hardware. In order to derive an efficient structure for BLASTN, we propose a reconfigurable architecture to accelerate the…

SpeedupSequence databaseHardware and ArchitectureComputer scienceSequence analysisGenomicsParallel computingElectrical and Electronic EngineeringData structureGenomic databasesSoftwareReconfigurable computingWord (computer architecture)IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Alignment-Free Sequence Comparison over Hadoop for Computational Biology

2015

Sequence comparison i.e., The assessment of how similar two biological sequences are to each other, is a fundamental and routine task in Computational Biology and Bioinformatics. Classically, alignment methods are the de facto standard for such an assessment. In fact, considerable research efforts for the development of efficient algorithms, both on classic and parallel architectures, has been carried out in the past 50 years. Due to the growing amount of sequence data being produced, a new class of methods has emerged: Alignment-free methods. Research in this ares has become very intense in the past few years, stimulated by the advent of Next Generation Sequencing technologies, since those…

SpeedupTheoretical computer scienceSettore INF/01 - InformaticaComputer scienceAlignment-free sequence comparison and analysis; Distributed computing; Hadoop; MapReduce; Software; Mathematics (all); Hardware and ArchitectureSequence alignmentContext (language use)Computational biologyDNA sequencingDistributed computingTask (project management)Alignment-free sequence comparison and analysisHadoopHardware and ArchitectureMathematics (all)Relevance (information retrieval)MapReducePattern matchingAlignment-free sequence comparison and analysiSoftware
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Design of the CGAL Spherical Kernel and application to arrangements of circles on a sphere

2009

International audience; This paper presents a CGAL kernel for algorithms manipulating 3D spheres, circles, and circular arcs. The paper makes three contributions. First, the mathematics underlying two non trivial predicates are presented. Second, the design of the kernel concept is developed, and the connexion between the mathematics and this design is established. In particular, we show how two different frameworks can be combined: one for the general setting, and one dedicated to the case where all the objects handled lie on a reference sphere. Finally, an assessment about the efficacy of the \sk\ is made through the calculation of the exact arrangement of circles on a sphere. On average …

SpheresCurved objectsCGALGeneric programming[INFO.INFO-CG]Computer Science [cs]/Computational Geometry [cs.CG]Constructions[ INFO.INFO-MS ] Computer Science [cs]/Mathematical Software [cs.MS]Geometric kernels[INFO.INFO-CG] Computer Science [cs]/Computational Geometry [cs.CG][INFO.INFO-MS] Computer Science [cs]/Mathematical Software [cs.MS][ INFO.INFO-CG ] Computer Science [cs]/Computational Geometry [cs.CG]RobustnessPredicates[INFO.INFO-MS]Computer Science [cs]/Mathematical Software [cs.MS]
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Hardware-accelerated spike train generation for neuromorphic image and video processing

2014

Recent studies concerning Spiking Neural Networks show that they are a powerful tool for multiple applications as pattern recognition, image tracking, and detection tasks. The basic functional properties of SNN reside in the use of spike information encoding as the neurons are specifically designed and trained using spike trains. We present a novel and efficient frequency encoding algorithm with Gabor-like receptive fields using probabilistic methods and targeted to FPGA for online pro-cessing. The proposed encoding is versatile, modular and, when applied to images, it is able to perform simple image transforms as edge detection, spot detection or removal, and Gabor-like filtering without a…

Spiking neural networkComputer sciencebusiness.industrySpike trainImage processingVideo processingEdge detectionNeuromorphic engineeringEncoding (memory)Computer visionSpike (software development)Artificial intelligencebusinessComputer hardware2014 IX Southern Conference on Programmable Logic (SPL)
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FPGA implementation of Spiking Neural Networks supported by a Software Design Environment

2011

Abstract This paper is focused on the creation of Spiking Neural Networks (SNN) in hardware due to their advantages for certain problem solving and their similarity to biological neural system. One of the main uses of this neural structure is pattern classification. The chosen model for the spiking neuron is the Spike Response Model (SRM). For SNN design and implementation, a software application has been developed to provide easy creation, simulation and automatic generation of the hardware model. VHDL was used for the hardware model. This paper describes the functionality of SNN and the design procedure followed to obtain a working neural system in both software and hardware. Designed VHD…

Spiking neural networkComputer sciencebusiness.industrymedicine.anatomical_structureSoftwareEmbedded systemPattern recognition (psychology)VHDLCode (cryptography)medicineSoftware designSpike (software development)NeuronbusinessField-programmable gate arraycomputercomputer.programming_languageIFAC Proceedings Volumes
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Fast spiking neural network architecture for low-cost FPGA devices

2012

Spiking Neural Networks (SNN) consist of fully interconnected computation units (neurons) based on spike processing. This type of networks resembles those found in biological systems studied by neuroscientists. This paper shows a hardware implementation for SNN. First, SNN require the inputs to be spikes, being necessary a conversion system (encoding) from digital values into spikes. For travelling spikes, each neuron interconnection is characterized by weights and delays, requiring an internal neuron processing by a Postsynaptic Potential (PSP) function and membrane potential threshold evaluation for a postsynaptic output spike generation. In order to model a real biological system by arti…

Spiking neural networkReduction (complexity)InterconnectionComputer sciencebusiness.industryComputationEncoding (memory)Real-time computingSpike (software development)Function (mathematics)Field-programmable gate arraybusinessComputer hardware7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)
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