Search results for "architecture"
showing 10 items of 3706 documents
Implementation of a new adaptive algorithm using fuzzy cost function and robust to impulsive noise
2012
Adaptive filters are used in a wide range of applications such as noise cancellation, system identification, and prediction. One of the main problems for theses filters is the impulsive noise as it generates algorithm unstability. This work shows the development, simulation and hardware implementation of a new algorithm robust to impulsive noise. Hardware implementation becomes essential in many cases where a real time execution, reduced size, or low power system is needed. An efficient hardware architecture is proposed and different optimizations for size and speed are developed: no need for control state machine, reduced computation requirements due to simplifications, etc. Furthermore, t…
From Arithmetic to Logic based AI: A Comparative Analysis of Neural Networks and Tsetlin Machine
2020
Neural networks constitute a well-established design method for current and future generations of artificial intelligence. They depends on regressed arithmetic between perceptrons organized in multiple layers to derive a set of weights that can be used for classification or prediction. Over the past few decades, significant progress has been made in low-complexity designs enabled by powerful hardware/software ecosystems. Built on the foundations of finite-state automata and game theory, Tsetlin Machine is increasingly gaining momentum as an emerging artificial intelligence design method. It is fundamentally based on propositional logic based formulation using booleanized input features. Rec…
New developments in simulation-based harbour crane training
2011
This paper presents the efforts that have been made during the development of a set of harbour training simulators to improve their quality. The paper focuses on two main research lines: the improvement of complex physical systems involved in the simulation and the analysis of hardware architecture solutions. Cable-based hoist systems and bulk materials are systems present in different harbour equipment and are usually simulated with poor quality due to their complexity. In this paper physics-based models for the interactive simulation of these systems are proposed and applied to real cases. Also, different hardware simulator architectures are analysed and different approaches are proposed …
A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks
2019
New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in la…
A Specialized Architecture for Color Image Edge Detection Based on Clifford Algebra
2013
Edge detection of color images is usually performed by applying the traditional techniques for gray-scale images to the three color channels separately. However, human visual perception does not differentiate colors and processes the image as a whole. Recently, new methods have been proposed that treat RGB color triples as vectors and color images as vector fields. In these approaches, edge detection is obtained extending the classical pattern matching and convolution techniques to vector fields. This paper proposes a hardware implementation of an edge detection method for color images that exploits the definition of geometric product of vectors given in the Clifford algebra framework to ex…
A readout unit for high rate applications
2002
The LHCb readout unit (RU) is a custom entry stage to the readout network of a data-acquisition or trigger system. It performs subevent building from multiple link inputs toward a readout network via a PCI network interface or alternatively toward a high-speed link, via an S-link interface. Incoming event fragments are derandomized, buffered and assembled into single subevents. This process is based on a low-overhead framing convention and matching of equal event numbers. Programmable logic is used both in the input and output stages of the RU module, which may be configured either as a data-link multiplexer or as entry stage to a readout or trigger network. All FPGAs are interconnected via…
Communication Interface Generation For HW/SW Architecture In The STARSoC Environment
2006
Mapping the application functionality to software and hardware requires automated methods to specify, generate and optimize the hardware, software, and the interface architectures between them. In this paper, we present a methodology flow to hardware-software communication synthesis for system-on-a-chip (SoC) design through STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-on-a-Chip) tool for rapid prototyping. Our concept consists of a set of hardware and software processes, described in C-code, communicates through the streams channels. This methodology consists in analyzing dependences of data between processes and synthesis a custom architecture to interface it. Firstly, we…
AMCAS: Advanced Methods for the Co-Design of Complex Adaptive Systems
2006
Abstract This work proposes a new approximation to design and program Complex Adaptive Systems (CAS), these systems comprise neural network, intelligent agents, genetic algorithms, support vector machines and artificial intelligence systems in general. Due to the complexity of such systems, it is necessary to build a design environment able to ease the design work, allowing reusability and easy migration to hardware and/or software. Ptolemy II is used as the base system to simulate and evaluate the designs with different Models of Computation so that an optimum decision about the hardware or software implementation platform can be taken.
Pathological voice analysis via digital signal processing
2015
The interest in pathological voice analysis for specific neurological diseases is growing up aiming to offer more Health-care tele monitoring services since new high performing electronic devices are available for the end-user. In this article we show some parameters that can be digitally extracted and analyzed from pathological voices, in order to find a distinctive sign of the Parkinson disease. As a result, we will show a parameter that gives some information about the Parkinson disease characterization, particularly for male patients. We will also discuss about the needed computational cost related to parameters extraction and elaboration, aiming to target a possible tough yet portable …
FADaC
2019
Solid state drives (SSDs) implement a log-structured write pattern, where obsolete data remains stored on flash pages until the flash translation layer (FTL) erases them. erase() operations, however, cannot erase a single page, but target entire flash blocks. Since these victim blocks typically store a mix of valid and obsolete pages, FTLs have to copy the valid data to a new block before issuing an erase() operation. This process therefore increases the latencies of concurrent I/Os and reduces the lifetime of flash memory. Data classification schemes identify data pages with similar update frequencies and group them together. FTLs can use this grouping to design garbage collection strategi…