Search results for "embedded system"
showing 10 items of 291 documents
Verification of JADE Agents Using ATL Model Checking
2015
It is widely accepted that the key to successfully developing a system is to produce a thorough system specification and design. This task requires an appropriate formal method and a suitable tool to determine whether or not an implementation conforms to the specifications. In this paper we present an advanced technique to analyse, design and debug JADE software agents, using Alternating-time Temporal Logic (ATL) which is interpreted over concurrent game structures, considered as natural models for compositions of open systems. In development of the proposed solution, we will use our original ATL model checker. In contrast to previous approaches, our tool permits an interactive or programma…
On the potential of NoC virtualization for multicore chips
2008
As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifted to the multicore paradigm and many-core processors are a reality. Within the context of these multi-core chips, three key metrics point themselves out as being of major importance, performance, fault-tolerance (including yield), and power consumption. A solution that optimizes all three of these metrics is challenging. As the number of cores increases the importance of the interconnection network-on-chip (NoC) grows as well, and chip designers should aim to optimize these three key metrics in the NoC context as …
Hardware Implementation of a Configurable Motion Estimator for Adjusting the Video Coding Performances
2012
International audience; Despite the diversity of video compression standard, the motion estimation still remains a key process which is used in most of them. Moreover, the required coding performances (bit-rate, PSNR, image spatial resolution, etc.) depend obviously of the application, the environment and the network communication. The motion estimation can therefore be adapted to fit with these performances. Meanwhile, the real time encoding is required in many applications. In order to reach this goal, we propose in this paper a hardware implementation of the motion estimator which enables the integer motion search algorithms to be modified and the fractional search and variable block siz…
Study of fibrosis induced by an implanted medical device
2014
National audience; This paper focuses on the study of fibrosis induced by an implanted medical device and explores the possibility of characterizing this process by in situ measurement of electrical impedance. The approach combines electrical and biological characterizations of fibrotic tissue, applied to electrodes implanted in animal models. A comparative study of electrical and biological parameters collected at the same time will enable the identification of an electrical marker of fibrosis development, which can be used for establishing a monitoring method. Adopting an interdisciplinary approach, intermediate embedded prototypes, autonomous and portable by animals, will be developed to…
Multiple modular very long instruction word processors based on field programmable gate arrays
2007
Modern field programmable gate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance very long instruction word (VLIW) processor core in an FPGA. This paper describes research results about enabling the DSP TMS320 C6201 model for real-time image processing applications by exploiting FPGA technology. We present a modular DSP C6201 VHDL model with a variable instruction set. We call this new development a minimum mandatory modules (M3) approach. Our goals are to keep the flexibility of DSP in order to shor…
Multithreaded Translation of Ptolemy II Designs on Multicore Platforms
2008
Ptolemy II is an open source environment for system design and test based on component data flow. This paradigm tries to make parallel systems more deterministic and understandable. In this work we propose a technique to translate designs developed with Ptolemy II, into multithreaded Java implementations on multicore platforms. We have chosen Java mainly because Ptolemy II is implemented in Java and then we get direct code reuse. The counterpart is a certain amount of overhead that we expect to be less relevant as Java runtime environment will evolve. The main goals are to produce efficient parallel simulators and software devices with competitive performance level. We show by means of an e…
Flexible VLIW processor based on FPGA for real-time image processing
2011
Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance Very Long Instruction Word (VLIW) processor core in an FPGA. With VLIW architecture, the processor effectiveness depends on the ability of compilers to provide sufficient Instruction Level Parallelism (ILP) from program code. This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors in order to shorten the developm…
A real-time network architecture for biometric data delivery in Ambient Intelligence
2012
Ambient Intelligent applications involve the deployment of sensors and hardware devices into an intelligent environment surrounding people, meeting users’ requirements and anticipating their needs (Ambi- ent Intelligence-AmI). Biometrics plays a key role in surveillance and security applications. Fingerprint, iris and voice/speech traits can be acquired by contact, contact-less, and at-a-distance sensors embedded in the environment. Biometric traits transmission and delivery is very critical and it needs real-time transmission net- work with guaranteed performance and QoS. Wireless networks become suitable for AmI if they are able to satisfy real-time communication and security system requi…
A Heterogeneous Sensor and Actuator Network Architecture for Ambient Intelligence
2014
One of the most important characteristics of a typical ambient intelligence scenario is the presence of a number of sensors and actuators that capture information about user preferences and activities. Such nodes, i.e., sensors and actuators, are often based on different technologies so that types of networks which are typically different coexist in a real system, for example, in a home or a building. In this chapter we present a heterogeneous sensor and actuator network architecture designed to separate network management issues from higher, intelligent layers. The effectiveness of the solution proposed here was evaluated using an experimental scenario involving the monitoring of an office…
A prototypal architecture of a IEEE 21451 network for smart grid applications based on power line communications
2015
This paper deals with the development of reliable measurement and communication devices and systems and their integration on a prototypal network architecture for smart grid applications, based on the use of narrowband power line communications (PLCs). The proposed solution is presented and discussed in the framework of the ISO/IEC/IEEE 21451 family of Standards. Currently, PLCs are not properly addressed by the aforesaid Standards; on the other hand, by including such issue, their guidelines could represent a common platform for the integration and interoperability of the proposed systems and devices. This would allow to exploit the benefits of the IEEE 21451 approach also for PLC-based sm…