Search results for "firmware"
showing 10 items of 27 documents
Experimental Assessment of the Backoff Behavior of Commercial IEEE 802.11b Network Cards
2007
It has been observed that different IEEE 802.11 commercial cards produced by different vendors experience different performance, either when accessing alone the channel, as well as when competing against each other. These differences persist also when thorough measurement methodologies (such as RF shielding, laptop rotation, etc) are applied, and alignment of the environmental factors (same laptop models, traffic generators, etc) is carried out. This paper provides an extensive experimental characterization of the backoff operation of six commercial NIC cards. It suggests a relevant methodological approach, namely a repeatable, well defined, set of experiments, for such a characterization. …
MAC design on real 802.11 devices: From exponential to Moderated Backoff
2016
In this paper we describe how a novel backoff mechanism called Moderated Backoff (MB), recently proposed as a standard extension for 802.11 networks, has been prototyped and experimentally validated on a commercial 802.11 card before being ratified. Indeed, for performance reasons, the time critical operations of MAC protocols, such as the backoff mechanism, are implemented into the card hardware/firmware and cannot be arbitrarily changed by third parties or by manufacturers only for experimental reasons. Our validation has been possible thanks to the availability of the so called Wireless MAC Processor (WMP), a prototype of a novel wireless card architecture in which MAC protocols can be p…
ATLAS TileCal Read Out Driver production
2007
The production tests of the 38 ATLAS TileCal Read Out Drivers (RODs) are presented in this paper. The hardware specifications and firmware functionality of the RODs modules, the test-bench and the test procedure to qualify the boards are described. Finally the performance results, the temperature studies and high rate tests are shown and discussed.
Development of a 3D CZT Spectrometer System with Digital Readout for Hard X/Gamma-Ray Astronomy
2019
We report on the development and of a complete X/γ rays detection system (10-1000 keV) based on CZT spectrometers with spatial resolution in three dimensions (3D) and a digital electronics acquisition chain. The prototype is made by packing four linear modules, each composed of one 3D CZT sensors. Each sensors is realized using a single spectroscopic graded CZT crystal of about 20×20×5 mm3. An electrode structure consisting of 12 collecting anodes with a pitch of 1.6 mm and 3 drift strips between each pair of anodes for 48 strips (0.15 mm wide) on the anodic side was adopted. The cathode is made of 10 strips with a pitch of 2 mm and orthogonal to anode side strips. Since the reading of the …
Insecure Firmware and Wireless Technologies as “Achilles’ Heel” in Cybersecurity of Cyber-Physical Systems
2022
In this chapter, we analyze cybersecurity weaknesses in three use-cases of real-world cyber-physical systems: transportation (aviation), remote explosives and robotic weapons (fireworks pyrotechnics), and physical security (CCTV). The digitalization, interconnection, and IoT-nature of cyber-physical systems make them attractive targets. It is crucial to ensure that such systems are protected from cyber attacks, and therefore it is equally important to study and understand their major weaknesses. peerReviewed
MAC-Engine
2011
In this demo, we prove that the flexibility supported by off-the-shelf IEEE 802.11 hardware can be significantly extended if we move the control of the MAC programming interface from the driver to the firmware, i.e. from the host CPU to the card CPU. To this purpose, we introduce the concept of MAC--Engine, that is an executor of Programmable Finite State Machines (PFSM) implemented at the firmware level: we show how the card itself can support different protocol logics thanks to PFSM bytecode representations that can be dynamically injected inside the card memory at run-time without incurring in down time issues or network disconnect events. We provide different PFSM examples in order to t…
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment
2011
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on th…
TileCal optical multiplexer board 9U prototype
2007
This paper presents the architecture and the status of the optical multiplexer board (OMB) for the ATLAS/LHC Tile hadronic calorimeter (TileCal). This board will analyze the front-end data CRC to prevent bit and burst errors produced by radiation. Besides, due to its position within the data acquisition chain it will be used to emulate front-end data for tests. The first two prototypes of the final OMB 9U version have been produced at CERN. Detailed design issues and manufacture features of these prototypes are described. These prototypes are being validated whereas some firmware developments are being implemented in the programmable devices of the board. Functional descriptions of the boar…
Wireless MAC processors: programming MAC protocols on commodity hardware
2012
Programmable wireless platforms aim at responding to the quest for wireless access flexibility and adaptability. This paper introduces the notion of wireless MAC processors. Instead of implementing a specific MAC protocol stack, Wireless MAC processors do support a set of Medium Access Control “commands” which can be run-time composed (programmed) through software-defined state machines, thus providing the desired MAC protocol operation. We clearly distinguish from related work in this area as, unlike other works which rely on dedicated DSPs or programmable hardware platforms, we experimentally prove the feasibility of the wireless MAC processor concept over ultra-cheap commodity WLAN hardw…
A High speed data link optimization for digitalized transfer to processing FPGA
2021
State-of-the-art arrays of detectors, that require digital processing, may have a sizeable number of digitalized signal links. This is the case in several experimental nuclear physics instruments. Moreover, the data rate of the sampled signals, defined primary by the signal bandwidth of the individual detectors, may not exhaust the capabilities of a single FPGA transceiver input. The preprocessing is usually carried out in a modern FPGA with transceiver data rate capabilities over 10Gbps. Moreover, cost effective FPGA have a limited number of transceivers for given FPGA processing capabilities. The investigation of a cost-effective and efficient solution to the mismatch between both data ra…