Search results for "gate"

Parallelizing Epistasis Detection in GWAS on FPGA and GPU-Accelerated Computing Systems

2015

This is a post-peer-review, pre-copyedit version of an article published in IEEE - ACM Transactions on Computational Biology and Bioinformatics. The final authenticated version is available online at: http://dx.doi.org/10.1109/TCBB.2015.2389958 [Abstract] High-throughput genotyping technologies (such as SNP-arrays) allow the rapid collection of up to a few million genetic markers of an individual. Detecting epistasis (based on 2-SNP interactions) in Genome-Wide Association Studies is an important but time consuming operation since statistical computations have to be performed for each pair of measured markers. Computational methods to detect epistasis therefore suffer from prohibitively lon…

Real Time Image Rotation Using Dynamic Reconfiguration

2002

Abstract Field programmable gate array (FPGA) components are widely used nowdays to implement various algorithms, such as digital filtering, in real time. The emergence of dynamically reconfigurable FPGAs made it possible to reduce the number of necessary resources to carry out an image-processing task (tasks chain). In this article, an image-processing application, image rotation, that exploits the FPGAs dynamic reconfiguration method is presented. This paper shows that the choice of an implementation, static or dynamic reconfiguration, depends on the nature of the application. A comparison is carried out between the dynamic and the static reconfiguration using two criteria: cost and perfo…

SoC-Based Implementation of the Backpropagation Algorithm for MLP

2008

The backpropagation algorithm used for the training of multilayer perceptrons (MLPs) has a high degree of parallelism and is therefore well-suited for hardware implementation on an ASIC or FPGA. However, most implementations are lacking in generality of application, either by limiting the range of trainable network topologies or by resorting to fixed-point arithmetic to increase processing speed. We propose a parallel backpropagation implementation on a multiprocessor system-on-chip (SoC) with a large number of independent floating-point processing units, controlled by software running on embedded processors in order to allow flexibility in the selection of the network topology to be traine…

Selective Harmonic Elimination in a 5-Level Single Phase Converter with FPGA Based Controller

2018

Multilevel converters are becoming popular in high-power applications such as motor drives, renewable energy systems and distribution systems. Among all modulation techniques, selective harmonic elimination methods offer high quality voltage waveforms with operations at low switching frequency, hence, they are especially suitable for high-power applications. In this paper, a new analytical expression for the SHE problem formulated for a five-level converter is introduced, which is able to calculate the exact value of the switching angles. After a mathematical description of the proposed approach, this manuscript reports simulation and experimental results and analysis showing achievable res…

Application based on dynamic reconfiguration of field-programmable gate arrays: JPEG 2000 arithmetic decoder

2005

This paper describes the implementation of a part of the JPEG 2000 algorithm (MQ decoder and arithmetic decoder) on a field-programmable gate array (FPGA) board by using dynamic reconfiguration. A comparison between static and dynamic reconfiguration is presented, and new analysis criteria (spatiotemporal efficiency, logic cost, and performance time) have been defined. The MQ decoder and arithmetic decoder are attractive for dynamic reconfiguration implementation in applications without parallel processing. This implementation is done on an architecture designed to study the dynamic reconfiguration of FPGAs: the ARDOISE architecture. The obtained implementation, based on four partial config…

A Measure of Concurrent Neural Firing Activity Based on Mutual Information

2021

Multiple methods have been developed in an attempt to quantify stimulus-induced neural coordination and to understand internal coordination of neuronal responses by examining the synchronization phenomena in neural discharge patterns. In this work we propose a novel approach to estimate the degree of concomitant firing between two neural units, based on a modified form of mutual information (MI) applied to a two-state representation of the firing activity. The binary profile of each single unit unfolds its discharge activity in time by decomposition into the state of neural quiescence/low activity and state of moderate firing/bursting. Then, the MI computed between the two binary streams is…

Measuring the agreement between brain connectivity networks.

2016

Investigating the level of similarity between two brain networks, resulting from measures of effective connectivity in the brain, can be of interest from many respects. In this study, we propose and test the idea to borrow measures of association used in machine learning to provide a measure of similarity between the structure of (un-weighted) brain connectivity networks. The measures here explored are the accuracy, Cohen's Kappa (K) and Area Under Curve (AUC). We implemented two simulation studies, reproducing two contexts of application that can be particularly interesting for practical applications, namely: i) in methodological studies, performed on surrogate data, aiming at comparing th…

Semantic and Logic Modeling of Disaster Simulation for Multi-agent Systems

2019

Experimental evaluation of privacy-preserving aggregation schemes on planetlab

2015

New pervasive technologies often reveal many sen- sitive information about users’ habits, seriously compromising the privacy and sometimes even the personal security of people. To cope with this problem, researchers have developed the idea of privacy-preserving data mining which refers to the possibility of releasing aggregate information about the data provided by multiple users, without any information leakage about individual data. These techniques have different privacy levels and communication costs, but all of them can suffer when some users’ data becomes inaccessible during the operation of the privacy preserving protocols. It is thus interesting to validate the applicability of such…

FPGA/LST-SW Encryption Module Implementation for Satellite Remote Sensing Secure Systems

2020

The need for security of data transmitted from satellites to the ground has increased. Therefore, the need for secure onboard systems is in great demand, particularly in satellite remote sensing missions. This paper describes an approach for a secure Field Programmable Gate Arrays (FPGA) implementation of the Land Surface Temperature Split Window (LST-SW) algorithm, with objective to meat real-time requirements, area optimization and achieved higher Throughput goals to be sufficient for a secure remote sensing satellite applications and missions. The system is designed using VHDL (VHSIC Hardware Description Language) in a Highlevel design method. The experimental results demonstrate that th…