Search results for "latency"
showing 10 items of 135 documents
In vivo impact of cytomegalovirus evasion of CD8 T-cell immunity: Facts and thoughts based on murine models
2010
Cytomegaloviruses (CMVs) co-exist with their respective host species and have evolved to avoid their elimination by the hosts' immune effector mechanisms and to persist in a non-replicative state, known as viral latency. There is evidence to suggest that latency is nevertheless a highly dynamic condition during which episodes of viral gene desilencing, which can be viewed as incomplete reactivations, cause intermittent antigenic activity that stimulates CD8 memory-effector T cells and drives their clonal expansion. These T cells are supposed to terminate reactivation before completion of the productive viral cycle. In this view, CMVs do not "evade" their respective host's immune response bu…
On the cellular mechanisms underlying working memory capacity in humans
2016
The cellular processes underlying individual differences in the Working Memory Capacity (WMC) of humans are essentially unknown. Psychological experiments suggest that subjects with lower working memory capacity (LWMC), with respect to subjects with higher capacity (HWMC), take more time to recall items from a list because they search through a larger set of items and are much more susceptible to interference during retrieval. However, a more precise link between psychological experiments and cellular properties is lacking and very difficult to investigate experimentally. In this paper, we investigate the possible underlying mechanisms at the single neuron level by using a computational mod…
Optimal signal selection of wide area damping controller considering time delay in multi-machine power system
2015
This paper presents a validation of selection process for selecting the most effective stabilizing signal to improve damping of inter area oscillations in a multi-machine power system by different signal selection methods. This paper also deals with wide area damping controller scheme compensating time latency of feedback signal in order to damp low frequency inter area oscillations in large power system. Pade approximation to time delay is used with controller synthesis. Eigenvector based coherent machine identification method has been adapted in this research for coherent area identification in multi-machine power system. The selected control signal is tested on the 4 machine 11 bus syste…
Second follow-up of a German cohort on childhood cancer incidence after exposure to postnatal diagnostic x-ray.
2019
Studies on children exposed to ionizing radiation by computed tomography (CT) indicate an increased risk of leukemia and central nervous system (CNS) tumors. Evidence of the risks associated with diagnostic X-ray examinations, the most frequent examination in pediatric radiology, in which the radiation dose is up to 750 times lower compared to CT examinations, is less clear.a#13; This study presents results of the second follow-up for the risk of childhood cancer in a cohort of children (alt;15 years) with diagnostic X-ray exposure at a large German hospital during 1976-2003 followed for additional 10 years until 2016.a#13; With a latency period of six months, 92,998 children contributed 79…
The Topological Processor for the future ATLAS Level-1 Trigger: From design to commissioning
2014
The ATLAS detector at the Large Hadron Collider (LHC) is designed to measure decay properties of high energetic particles produced in the proton-proton collisions. During its first run, the LHC collided proton bunches at a frequency of 20 MHz, and therefore the detector required a Trigger system to efficiently select events down to a manageable event storage rate of about 400 Hz. By 2015 the LHC instantaneous luminosity will be increased up to 3×1034cm−2s−1: this represents an unprecedented challenge faced by the ATLAS Trigger system. To cope with the higher event rate and efficiently select relevant events from a physics point of view, a new element will be included in the Level-1 Trigger …
Pre-production validation of the ATLAS level-1 calorimeter trigger system
2006
The Level-1 Calorimeter Trigger is a major part of the first stage of event selection for the ATLAS experiment at the LHC. It is a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of trigger objects and energy sums. Prototypes of all module types have been undergoing intensive testing before final production during 2005. Verification of their correct operation has been performed stand-alone and in the ATLAS test-beam at CERN. Results from these investigations will be presented, along …
Time-Space Domain Availability Analysis Under Reliability Impairments
2019
Availability and reliability are two essential metrics for the design, deployment, and operation of future ultra-reliable low latency communication (URLLC) networks. Despite a vast amount of research efforts toward URLLC, very little attention has been made on the ultra-reliable communication (URC) aspect of URLLC from a dependability perspective. As an effort toward achieving anytime and anywhere communication, this letter consolidates a dependability theory-based availability concept for individual users by taking into account reliability impairments that affect URC in both spatial and temporal domains . To this end, we perform per-user availability analysis by considering channel status …
Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA
2021
Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant appli…
Priority-based initial access for URLLC traffic in massive IoT networks: Schemes and performance analysis
2020
Abstract At a density of one million devices per square kilometer, the10’s of billions of devices, objects, and machines that form a massive Internet of things (mIoT) require ubiquitous connectivity. Among a massive number of IoT devices, a portion of them require ultra-reliable low latency communication (URLLC) provided via fifth generation (5G) networks, bringing many new challenges due to the stringent service requirements. Albeit a surge of research efforts on URLLC and mIoT, access mechanisms which include both URLLC and massive machine type communications (mMTC) have not yet been investigated in-depth. In this paper, we propose three novel schemes to facilitate priority-based initial …
Three-dimensional matching based resource provisioning for the design of low-latency heterogeneous IoT networks
2019
Internet-of-Things (IoT) is a networking architecture where promising, intelligent services are designed via leveraging information from multiple heterogeneous sources of data within the network. However, the availability of such information in a timely manner requires processing and communication of raw data collected from these sources. Therefore, the economic feasibility of IoT-enabled networks relies on the efficient allocation of both computational and communication resources within the network. Since fog computing and 5G cellular networks approach this problem independently, there is a need for joint resource-provisioning of both communication and computational resources in the networ…