Search results for "processo"

showing 10 items of 648 documents

Improving the performance of CAR systems based on mobile phones

2013

Collaborative Augmented Reality (CAR) systems allow multiple users to share a real work environment including computer-generated images in real time. Currently, the hardware features of most mobile phones makes them a natural platform for CAR systems. However, the wide variety of these hardware features can have important effects on the performance of the mobile CAR applications. This thesis proposes a performance characterization and improvement of CAR systems based on mobile phones. The research results, at the time of writing this paper, shows that a CAR system using mobile phones as clients and with a single server can support up to one thousand clients while providing interactive respo…

Mobile processorMultimediaComputer scienceIMT Advanced010401 analytical chemistryMobile computing020207 software engineeringMobile Web02 engineering and technologyMobile communications over IPcomputer.software_genre01 natural sciences0104 chemical sciencesComputerSystemsOrganization_MISCELLANEOUSMobile station0202 electrical engineering electronic engineering information engineeringMobile searchMobile technologycomputer
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Mobile Search - Social Network Search Using Mobile Devices Demonstration

2008

Mobile search prototype demonstrates the possibilities of social network search in N800 mobile devices. Search is initiated from a N800 mobile device to search the contacts in mobile device's addressbook. The contacts can be other N800 mobile devices running mobile Web server or normal Web servers in the Internet with Drupal content management system. Mobile device users can select which of their personal information such as phone numbers, calendar data etc. to share via a mobile Web server. The proposed search mechanism has many benefits compared to centralized Web search engines like Google. The search can locate information which is not referenced anywhere and thus allows hidden or rare …

Mobile processorWeb serverMobile identification numberComputer scienceMobile computingMobile WebMobile communications over IPcomputer.software_genreWorld Wide WebPublic land mobile networkServerMobile stationMobile databaseMobile paymentMobile searchMobile technologyGSM servicesRadio access networkSocial networkbusiness.industrySearch analyticsThe InternetbusinesscomputerPersonally identifiable informationMobile deviceComputer network2008 5th IEEE Consumer Communications and Networking Conference
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Mobile Encounter Networks and Their Applications

2008

This article presents mobile encounter networks (MENs), which emerge when mobile devices come across each other and form a temporary connection between them using a common short-range radio technology. Local information exchanges between mobile devices results in a broadcast diffusion of information to other users of the network with a delay. Gasoline price comparison system (GPCS), which delivers newest gasoline prices to mobile users using mobile encounter information diffusion, is described as well as other application areas where MENs could be used. The feasibility of building MENs using bluetooth is tested with the BlueCheese mobile encounter network middleware and it is found that the…

Mobile radioMobile processorMobile identification numberComputer scienceMobile computingMobile Weblaw.inventionPublic land mobile networkBluetoothlawMobile stationMobile phone signalMobile databaseMobile paymentMobile searchMobile technologyGSM servicesRadio access networkbusiness.industryIMT AdvancedMobile broadbandMiddlewareSmall cellTelecommunicationsbusinessMobile deviceComputer network2008 5th IEEE Consumer Communications and Networking Conference
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One-dimensional hydrodynamic modeling of coronal plasmas on transputer arrays

1990

Abstract We describe a concurrent implementation of the Palermo-Harvard hydrodynamic code on cost-effective and modularity expandable transputer arrays. We have tested the effectiveness of our approach by simulating an already well-studied compact solar-flare model on different transputer configurations and compared their performances with those of other machines. We have found that the speed of the concurrent program on a 16-T800 transputers array is ~1/9 of that of the equivalent code optimized for a CRAY X-MP/48. This work clearly shows that transputer-based arrays provide locally available high computing-power tools to extend the investigation of compact solar flares and similar astroph…

Modularity (networks)Partial differential equationComputerSystemsOrganization_COMPUTERSYSTEMIMPLEMENTATIONParallel processing (DSP implementation)Hardware and ArchitectureComputer scienceTransputerCode (cryptography)General Physics and AstronomyPlasmaComputerSystemsOrganization_PROCESSORARCHITECTURESAlgorithmComputational scienceComputer Physics Communications
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"Mal governo" e controllo nella Monarchia Spagnola: il processo di residencia a Carmine Nicola Caracciolo, viceré del Perù

2020

In recent decades, the historiographical debate on the political nature of the Spanish Monarchy has been enriched thanks to an important corpus of research dedicated to the reconstruction of the multiple forms of “remote government”, and to the study of the tools adopted by the sovereign to exercise greater control over ministers and officers who held their careers far from the beating heart of the Monarchy. In this context, the study of “corruption” practices and attempts to stem them has opened up new interpretative perspectives, especially with reference to the analysis of the residencia processes to which ministers and officials of the West Indies were subjected. The essay, through the …

Monarchia Spagnola governo a distanza processo di residencia principe di SantobuonoSettore M-STO/02 - Storia Moderna
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On the potential of NoC virtualization for multicore chips

2008

As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifted to the multicore paradigm and many-core processors are a reality. Within the context of these multi-core chips, three key metrics point themselves out as being of major importance, performance, fault-tolerance (including yield), and power consumption. A solution that optimizes all three of these metrics is challenging. As the number of cores increases the importance of the interconnection network-on-chip (NoC) grows as well, and chip designers should aim to optimize these three key metrics in the NoC context as …

Moore's lawMulti-core processorComputer sciencebusiness.industrymedia_common.quotation_subjectContext (language use)Fault toleranceVirtualizationcomputer.software_genreNetwork on a chipEmbedded systemKey (cryptography)Routing (electronic design automation)businesscomputermedia_common
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The Acts project: track reconstruction software for HL-LHC and beyond

2019

The reconstruction of trajectories of the charged particles in the tracking detectors of high energy physics experiments is one of the most difficult and complex tasks of event reconstruction at particle colliders. As pattern recognition algorithms exhibit combinatorial scaling to high track multiplicities, they become the largest contributor to the CPU consumption within event reconstruction, particularly at current and future hadron colliders such as the LHC, HL-LHC and FCC-hh. Current algorithms provide an extremely high standard of physics and computing performance and have been tested on billions of simulated and recorded data events. However, most algorithms were first written 20 year…

Multi-core processor010308 nuclear & particles physicsEvent (computing)track data analysisPhysicsQC1-999Complex event processing01 natural sciencesprogrammingComputing and ComputersComputer engineeringMultithreading0103 physical sciencesmultiprocessorCERN LHC Coll: upgradeProgramming paradigmThread safety[INFO]Computer Science [cs]data managementReference implementation010306 general physicsnumerical calculationsperformanceactivity reportEvent reconstruction
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Concept and Development of Modular VLIW Processor Based on FPGA

2010

Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance VLIW processor core in an FPGA. Architecture based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance level in embedded system. In VLIW architecture, the effectiveness of these processors depends on the ability of compilers to provide sufficient instruction level parallelism(ILP) in program code. Using advanced compiler technology could take these functions, This paper describes research resu…

Multi-core processorAssembly languagebusiness.industryComputer scienceHardware description languageModular designcomputer.software_genreComputer architectureVery long instruction wordVHDLCompilerInstruction-level parallelismbusinesscomputercomputer.programming_language2010 Second International Conference on Computer and Network Technology
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Multiple modular very long instruction word processors based on field programmable gate arrays

2007

Modern field programmable gate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance very long instruction word (VLIW) processor core in an FPGA. This paper describes research results about enabling the DSP TMS320 C6201 model for real-time image processing applications by exploiting FPGA technology. We present a modular DSP C6201 VHDL model with a variable instruction set. We call this new development a minimum mandatory modules (M3) approach. Our goals are to keep the flexibility of DSP in order to shor…

Multi-core processorComputer sciencebusiness.industryReconfigurabilityModular designAtomic and Molecular Physics and OpticsComputer Science ApplicationsInstruction setParallel processing (DSP implementation)Computer architectureVery long instruction wordEmbedded systemVHDLHardware_ARITHMETICANDLOGICSTRUCTURESElectrical and Electronic EngineeringField-programmable gate arraybusinesscomputercomputer.programming_languageJournal of Electronic Imaging
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Enhancing the Sniper Simulator with Thermal Measurement

2014

This paper presents the enhancement of the Sniper multicore / manycore simulator with thermal measurement possibilities using the HotSpot simulator. We present a plugin that interacts with Sniper to retrieve simulation data (integration areas and power consumptions) and calls HotSpot to compute the corresponding thermal results. The plugin also builds a two dimensional floorplan for the simulated microarchitecture. Furthermore we plan to integrate the simulation methodology presented here into an automatic design space exploration process using the multi-objective optimization tool called FADSE. Keywords—multicore; simulator; power consumption; thermal; HotSpot; Sniper

Multi-core processorEngineeringComputer architecture simulatorbusiness.industryDesign space explorationReal-time computingHardware_PERFORMANCEANDRELIABILITYcomputer.software_genreFloorplanMicroarchitecturePower consumptionThermalHardware_INTEGRATEDCIRCUITSPlug-inbusinesscomputerSimulation
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