0000000000006039
AUTHOR
Esmaeil Najafi Aghdam
showing 2 related works from this author
Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC
2019
Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved channels, together with its hardware implementation. The proposed algorithm provides low computation burden and high performance. It is based on the simplified representation of the coefficients of the Lagrange interpolator. Simulation results show that it can suppress error tones in all of the Nyquist band. Results show that, for a four-channel TIADC with 10-bit resolution, the proposed algorithm improves the signal to noise and distortion ratio (SN…
Low complexity digital background calibration algorithm for the correction of timing mismatch in time-interleaved ADCs
2019
Abstract A low-complexity post-processing algorithm to estimate and compensate for timing skew error in a four-channel time-interleaved analog to digital converter (TIADC) is presented in this paper, together with its hardware implementation. The Lagrange interpolator is used as the reconstruction filter which alleviates online interpolator redesign by using a simplified representation of coefficients. Simulation results show that the proposed algorithm can suppress error tones for input signal frequency from 0 to 0.4 f s . The proposed structure has, at least, 41% reduction in the number of required multipliers. Implementation of the algorithm, for a four-channel 10-bit TIADC, show that, f…