0000000000115575

AUTHOR

Samuel Rodrigo

showing 4 related works from this author

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing

2010

The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge.In this paper, uLBDR (Universal Logic-Based Distributed Routing) is proposed as an efficient logic-based mechanism that adapts to any irregular topology derived from 2D meshes, being an alter…

010302 applied physicsStatic routingDynamic Source Routingnetwork on chip; routing; manufacturing faultComputer sciencebusiness.industryRouting tableDistributed computingPolicy-based routing02 engineering and technology01 natural sciences020202 computer hardware & architecturenetwork on chipRouting domainLink-state routing protocolrouting0103 physical sciencesMultipath routing0202 electrical engineering electronic engineering information engineeringmanufacturing faultbusinessHierarchical routingComputer network
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Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems

2011

[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of usi…

RouterComputer scienceRouting tableDistributed computing02 engineering and technologyMPSoCNetwork topology01 natural sciencesNetworks-on-chip0103 physical sciences0202 electrical engineering electronic engineering information engineeringElectrical and Electronic EngineeringRouting010302 applied physicsStatic routingbusiness.industryComputer Graphics and Computer-Aided Design020202 computer hardware & architectureFault-toleranceARQUITECTURA Y TECNOLOGIA DE COMPUTADORESNetwork on a chip13. Climate actionLogic designEmbedded systemScalabilityMultipath routingbusinessSoftwareIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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On the potential of NoC virtualization for multicore chips

2008

As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifted to the multicore paradigm and many-core processors are a reality. Within the context of these multi-core chips, three key metrics point themselves out as being of major importance, performance, fault-tolerance (including yield), and power consumption. A solution that optimizes all three of these metrics is challenging. As the number of cores increases the importance of the interconnection network-on-chip (NoC) grows as well, and chip designers should aim to optimize these three key metrics in the NoC context as …

Moore's lawMulti-core processorComputer sciencebusiness.industrymedia_common.quotation_subjectContext (language use)Fault toleranceVirtualizationcomputer.software_genreNetwork on a chipEmbedded systemKey (cryptography)Routing (electronic design automation)businesscomputermedia_common
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An Efficient Implementation of Distributed Routing Algorithms for NoCs

2008

The design of NoCs for multi-core chips introduces new design constraints like power consumption, area, and ultra low latencies. Although 2D meshes are preferred, heterogeneous blocks, fabrication faults, reliability issues, and chip virtualization may lead to the need of irregular topologies or regions. In this situation, efficient routing becomes a challenge. Although the use of routing tables at switches is flexible, it does not scale in terms of latency and area due to its memory requirements. LBDR (logic-based distributed routing) is proposed as a new routing method that removes the need of using routing tables at all. LBDR enables the implementation of many routing algorithms on most …

Static routingDynamic Source RoutingZone Routing ProtocolComputer sciencebusiness.industryDistributed computingRouting tableEnhanced Interior Gateway Routing ProtocolPolicy-based routingLink-state routing protocolMultipath routingHardware_INTEGRATEDCIRCUITSbusinessComputer networkSecond ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
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