0000000000115577

AUTHOR

Davide Bertozzi

showing 3 related works from this author

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing

2010

The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge.In this paper, uLBDR (Universal Logic-Based Distributed Routing) is proposed as an efficient logic-based mechanism that adapts to any irregular topology derived from 2D meshes, being an alter…

010302 applied physicsStatic routingDynamic Source Routingnetwork on chip; routing; manufacturing faultComputer sciencebusiness.industryRouting tableDistributed computingPolicy-based routing02 engineering and technology01 natural sciences020202 computer hardware & architecturenetwork on chipRouting domainLink-state routing protocolrouting0103 physical sciencesMultipath routing0202 electrical engineering electronic engineering information engineeringmanufacturing faultbusinessHierarchical routingComputer network
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Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems

2011

[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of usi…

RouterComputer scienceRouting tableDistributed computing02 engineering and technologyMPSoCNetwork topology01 natural sciencesNetworks-on-chip0103 physical sciences0202 electrical engineering electronic engineering information engineeringElectrical and Electronic EngineeringRouting010302 applied physicsStatic routingbusiness.industryComputer Graphics and Computer-Aided Design020202 computer hardware & architectureFault-toleranceARQUITECTURA Y TECNOLOGIA DE COMPUTADORESNetwork on a chip13. Climate actionLogic designEmbedded systemScalabilityMultipath routingbusinessSoftwareIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

2010

Nowadays, system designers have adopted Networks-on-Chip as communication infrastructure of general-purpose tile-based Multi-Processor System-on-Chip (MPSoC). Such decision implies that a certain topology has to be selected to efficiently interconnect many cores on the chip. To ease such a choice, the networking literature offers a plethora of works about topology analysis and characterization for the off-chip domain. However, theoretical parameters and many intuitive assumptions of such off-chip networks do not necessarily hold when a topology is laid out on a 2D silicon surface. This is due to the distinctive features of silicon technology design pitfalls. This work is a first milestone t…

010302 applied physicsTopology exploration; Network-on-ChipInterconnectionComputer sciencebusiness.industryDistributed computingLogical topologyTopology explorationTopology (electrical circuits)02 engineering and technologyMPSoCNetwork topology01 natural sciencesPipeline (software)020202 computer hardware & architectureNetwork on a chip0103 physical sciences0202 electrical engineering electronic engineering information engineeringNetwork-on-ChipbusinessDesign technologyComputer network
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