0000000000115578

AUTHOR

Antoni Roca

showing 3 related works from this author

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing

2010

The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge.In this paper, uLBDR (Universal Logic-Based Distributed Routing) is proposed as an efficient logic-based mechanism that adapts to any irregular topology derived from 2D meshes, being an alter…

010302 applied physicsStatic routingDynamic Source Routingnetwork on chip; routing; manufacturing faultComputer sciencebusiness.industryRouting tableDistributed computingPolicy-based routing02 engineering and technology01 natural sciences020202 computer hardware & architecturenetwork on chipRouting domainLink-state routing protocolrouting0103 physical sciencesMultipath routing0202 electrical engineering electronic engineering information engineeringmanufacturing faultbusinessHierarchical routingComputer network
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On the impact of within-die process variation in GALS-Based NoC Performance

2012

[EN] Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes some unpredictability in manufactured devices because of process variation. In NoCs, variability may affect links and routers causing them not to match the parameters established at design time. In this paper, we first analyze the way that manufacturing deviations affect the components of a NoC by applying a new comprehensive and detailed within-die variability model to 200 instances of an 8¿8 mesh NoC synthesized using 45 nm technology. Later, we show that GALS-based NoCs pr…

Engineering02 engineering and technology01 natural sciencesExecution timeDie (integrated circuit)Networks-on-chipReduction (complexity)0103 physical sciencesSynchronization (computer science)0202 electrical engineering electronic engineering information engineeringGALSElectrical and Electronic Engineering010302 applied physicsbusiness.industryChipComputer Graphics and Computer-Aided Design020202 computer hardware & architectureProcess variationARQUITECTURA Y TECNOLOGIA DE COMPUTADORESProcess variationNetwork on a chipLogic gateEmbedded systembusinessSoftware
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Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems

2011

[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of usi…

RouterComputer scienceRouting tableDistributed computing02 engineering and technologyMPSoCNetwork topology01 natural sciencesNetworks-on-chip0103 physical sciences0202 electrical engineering electronic engineering information engineeringElectrical and Electronic EngineeringRouting010302 applied physicsStatic routingbusiness.industryComputer Graphics and Computer-Aided Design020202 computer hardware & architectureFault-toleranceARQUITECTURA Y TECNOLOGIA DE COMPUTADORESNetwork on a chip13. Climate actionLogic designEmbedded systemScalabilityMultipath routingbusinessSoftwareIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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