6533b7d3fe1ef96bd1260a51
RESEARCH PRODUCT
On the impact of within-die process variation in GALS-Based NoC Performance
Jose FlichCarles HernandezJosé DuatoFederico SillaAntoni Rocasubject
Engineering02 engineering and technology01 natural sciencesExecution timeDie (integrated circuit)Networks-on-chipReduction (complexity)0103 physical sciencesSynchronization (computer science)0202 electrical engineering electronic engineering information engineeringGALSElectrical and Electronic Engineering010302 applied physicsbusiness.industryChipComputer Graphics and Computer-Aided Design020202 computer hardware & architectureProcess variationARQUITECTURA Y TECNOLOGIA DE COMPUTADORESProcess variationNetwork on a chipLogic gateEmbedded systembusinessSoftwaredescription
[EN] Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes some unpredictability in manufactured devices because of process variation. In NoCs, variability may affect links and routers causing them not to match the parameters established at design time. In this paper, we first analyze the way that manufacturing deviations affect the components of a NoC by applying a new comprehensive and detailed within-die variability model to 200 instances of an 8¿8 mesh NoC synthesized using 45 nm technology. Later, we show that GALS-based NoCs present communication bottlenecks under process variation which cannot be avoided by using just device-level solutions but higher level architectural approaches are required. Therefore, to overcome this performance reduction, we draft a novel architectural approach, called performance domains, intended to reduce the negative impact of variability on application execution time. This mechanism is suitable when several applications are simultaneously running in the CMP chip.
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2012-02-01 |