0000000000115579

AUTHOR

Federico Silla

showing 6 related works from this author

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing

2010

The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge.In this paper, uLBDR (Universal Logic-Based Distributed Routing) is proposed as an efficient logic-based mechanism that adapts to any irregular topology derived from 2D meshes, being an alter…

010302 applied physicsStatic routingDynamic Source Routingnetwork on chip; routing; manufacturing faultComputer sciencebusiness.industryRouting tableDistributed computingPolicy-based routing02 engineering and technology01 natural sciences020202 computer hardware & architecturenetwork on chipRouting domainLink-state routing protocolrouting0103 physical sciencesMultipath routing0202 electrical engineering electronic engineering information engineeringmanufacturing faultbusinessHierarchical routingComputer network
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Network Reconfiguration Suitability for Scientific Applications

2008

This paper analyzes the communication pattern of several scientific applications and how they can make profit of network reconfiguration in order to adapt network topology to the communication needs so that total execution time is reduced. By using an analysis methodology based on real application executions, we study the variation of the required communication bandwidth with time and also the global interprocedural communication patterns. Results show that required bandwidth between each pair of processes does not significantly fluctuates, leading to a constant use of the links and therefore discouraging dynamic reconfigurations of the network during execution time. Nevertheless, the group…

Wireless ad hoc networkComputer sciencebusiness.industryDistributed computingMessage passingMessage Passing InterfaceSystem on a chipNetwork reconfigurationbusinessNetwork topologyNetwork simulationComputer network2008 37th International Conference on Parallel Processing
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On the impact of within-die process variation in GALS-Based NoC Performance

2012

[EN] Current integration scales allow designing chip multiprocessors (CMP), where cores are interconnected by means of a network-on-chip (NoC). Unfortunately, the small feature size of current integration scales causes some unpredictability in manufactured devices because of process variation. In NoCs, variability may affect links and routers causing them not to match the parameters established at design time. In this paper, we first analyze the way that manufacturing deviations affect the components of a NoC by applying a new comprehensive and detailed within-die variability model to 200 instances of an 8¿8 mesh NoC synthesized using 45 nm technology. Later, we show that GALS-based NoCs pr…

Engineering02 engineering and technology01 natural sciencesExecution timeDie (integrated circuit)Networks-on-chipReduction (complexity)0103 physical sciencesSynchronization (computer science)0202 electrical engineering electronic engineering information engineeringGALSElectrical and Electronic Engineering010302 applied physicsbusiness.industryChipComputer Graphics and Computer-Aided Design020202 computer hardware & architectureProcess variationARQUITECTURA Y TECNOLOGIA DE COMPUTADORESProcess variationNetwork on a chipLogic gateEmbedded systembusinessSoftware
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LSOM: A Link State protocol Over MAC addresses for metropolitan backbones using Optical Ethernet switches

2003

This paper presents a new protocol named "Link State Over MAC" (LSOM) for Optical Ethernet switches to allow the use of active loop topologies, like meshes, in Metropolitan Area Networks (MAN) or even Wide Area Networks (WAN) backbone. In this respect, LSOM is an alternative to a ring topology as proposed in draft IEEE 802.17 Resilient Packet Ring (RPR) or a tree topology using IEEE802. 1D Rapid Spanning Tree Protocol (RSTP). LSOM provides higher scalability and is able to achieve better bandwidth utilization and lower latency than RSTP and RPR. Simulation results for 4-node and 9-node topologies show that LSOM can improve throughput over RPR by a factor of up to 1.7. Furthermore, full free…

Ethernetbusiness.industryComputer scienceDistributed computingResilient Packet RingSynchronous optical networkingComputerSystemsOrganization_COMPUTER-COMMUNICATIONNETWORKSRing networkThroughputNetwork topologySpanning Tree ProtocolOptical switchMetropolitan areaLink-state routing protocolbusinessComputer networkSecond IEEE International Symposium on Network Computing and Applications, 2003. NCA 2003.
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Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems

2011

[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of usi…

RouterComputer scienceRouting tableDistributed computing02 engineering and technologyMPSoCNetwork topology01 natural sciencesNetworks-on-chip0103 physical sciences0202 electrical engineering electronic engineering information engineeringElectrical and Electronic EngineeringRouting010302 applied physicsStatic routingbusiness.industryComputer Graphics and Computer-Aided Design020202 computer hardware & architectureFault-toleranceARQUITECTURA Y TECNOLOGIA DE COMPUTADORESNetwork on a chip13. Climate actionLogic designEmbedded systemScalabilityMultipath routingbusinessSoftwareIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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On the development of a communication-aware task mapping technique

2004

Clusters have become a very cost-effective platform for high-performance computing. In these systems, although currently existing networks actually provide enough bandwidth for the existing applications and workstations, the trend is towards the interconnection network becoming the system bottleneck. Therefore, in the future, scheduling strategies will have to take into account the communication requirements of the applications and the communication bandwidth that the network can offer. One of the key issues in these strategies is the task mapping technique used when the network becomes the system bottleneck.In this paper, we propose a communication-aware mapping technique that tries to mat…

InterconnectionWorkstationbusiness.industryComputer scienceDistributed computingLoad balancing (computing)BottleneckNetwork traffic controllaw.inventionScheduling (computing)Network simulationHardware and ArchitecturelawTimestampbusinessSoftwareComputer networkJournal of Systems Architecture
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