0000000000146952
AUTHOR
F. Carrio
Evaluation of a Commercial PhotoDiode Array for Radiation Detectors Readout
The aim of the present work is the characterization of the new S8866-128-02 PhotoDiode (PD) array from Hamamatsu Photonics. This work includes the implementation of a readout system as well as electronic noise estimation in PDs under several conditions varying integration times and clock frequencies.
Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator
A potential upgrade for the front-end electronics and signal digitization and data acquisition system of the ATLAS hadron calorimeter for the high luminosity Large Hadron Collider (HL-LHC) is described. A Demonstrator is being built to readout a slice of the TileCal detector. The on-detector electronics includes up to 48 Analog Front-end Boards for PMT analog signal processing, 4 Main Boards for data digitization and slow controls, 4 Daughter Boards with high speed optical links to interface the on-detector and off-detector electronics. Two super readout driver boards are used for off-detector data acquisition and fulfilling digital trigger.\n The ATLAS Tile Calorimeter on-detector electron…
Functional super Read-Out Driver demonstrator for the Phase II Upgrade of the ATLAS Tile Calorimeter
This work presents the implementation of a functional super Read-Out Driver (sROD) demonstrator for the Phase II Upgrade of the ATLAS Tile Calorimeter (TileCal) in the LHC experiment. The proposed front-end for the Phase II Upgrade communicates with back-end electronics using a multifiber optical connector with a data rate of 57.6 Gbps using the GBT protocol. This functional sROD demonstrator aims to help in the understanding of the problems that could arise in the upgrade of back-end electronics. The demonstrator is composed of three different boards that have been developed in the framework of ATLAS activities: the Optical Multiplexer Board (OMB), the Read-Out Driver (ROD) and the Optical…
FPGA implementation of a deep learning algorithm for real-time signal reconstruction in particle detectors under high pile-up conditions
The analog signals generated in the read-out electronics of particle detectors are shaped prior to the digitization in order to improve the signal to noise ratio (SNR). The real amplitude of the analog signal is then obtained using digital filters, which provides information about the energy deposited in the detector. The classical digital filters have a good performance in ideal situations with Gaussian electronic noise and no pulse shape distortion. However, high-energy particle colliders, such as the Large Hadron Collider (LHC) at CERN, can produce multiple simultaneous events, which produce signal pileup. The performance of classical digital filters deteriorates in these conditions sinc…
Optical Link Card Design for the Phase II Upgrade of TileCal Experiment
This paper presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment. This board, that is part of the evaluation of different technologies for the final choice in the next years, is designed as a mezzanine that can work independently or be plugged in the optical multiplexer board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gb/s and one SFP optical connector for lower speeds and compatibility with existing hardware as the read out driver. All processing is done in a Stratix II GX field-programmable gate array (FPGA). Details are given on th…
A capacitor selector tool for on-board PDN designs in multigigabit applications
This paper presents a capacitor selector software tool for a proper on-board Power Distribution Network (PDN) design in those high-speed applications which have strict requirements on voltage noise up to the first hundreds of megahertz. Current commercial tools for PDN design only offer a manual choice of the capacitor value and their number simulating the board impedance profile. This manual resolution becomes very hard when the design has high power consumption and noise requirements are very strict. The aim of this software is to solve a basic on-board PDN design minimizing the number of "change simulate-analyze" iterations that have to be carried out in the manual PDN design. This softw…
The sROD demonstrator for the ATLAS Tile Calorimeter Upgrade
This work presents the early design of the super Read-Out Driver (sROD) demonstrator board for the Tile Calorimeter Demonstrator project. This project aims to test the new readout electronics architecture for the Phase 2 Upgrade of the ATLAS Tile Calorimeter, replacing the front-end electronics of one complete drawer with the new electronics during the Long Shutdown 2013, in order to evaluate its performance. The sROD demonstrator board will receive and process data from 48 channels. Moreover the sROD demonstrator board will send preprocessed data to the present trigger system, and will transmit trigger control and timing information (TTC) and Detector Control System (DCS) commands to the f…
Development of an optical link card for the upgrade phase II of TileCal experiment
This work presents the design of an optical link card developed in the frame of the R&D activities for the phase 2 upgrade of the TileCal experiment as part of the evaluation of different technologies for the final choice in the next two years. The board is designed as a mezzanine which can work independently or plugged in the Optical Multiplexer Board of the TileCal backend electronics. It includes two SNAP 12 optical connectors able to transmit and receive up to 75 Gbps and one SFP optical connector for lower speeds and compatibility with existing hardware as the Read Out Driver. All processing is done in a Stratix II GX FPGA. Details are given on the hardware design including signal and …
Evaluation of a commercial APD array (Avalanche PhotoDiode) for a readout detector in a hadrontherapy beam characterization application
The aim of the present work is the characterization of the S8898–128–02 Avalanche PhotoDiode array (APDs) from Hamamatsu Photonics. This work includes the implementation of a readout system as well as electronic noise estimation in APDs under several conditions varying integration times and clock frequencies.
Basic Concepts of Power Distribution Network Design for High-Speed Transmission
This paper tries to gather the Power Distribution Network (PDN) techniques used to preserve power integrity in PCB designs when transmitting data rates over 6 Gbps using the newest commercial optical modules. The PDN design described allows for proper impedance control of the power supply with the appropriate choice of the number, location and values of capacitors. This method needs the knowledge of the electrical RLC model of the regulators, copper planes, capacitors and vias used in the PCB. A particular case of PDN design will be presented for a module using one SNAP12 optical transmitter and one receiver connected to an Altera Stratix II GX FPGA. This board is designed to work with data…
Optimal filtering algorithm implementation in FPGAs for the ATLAS TileCal Read-Out drivers
TileCal is the hadronic calorimeter of the ATLAS experiment in the LHC (CERN). Its Read-Out Drivers (RODs) process, in real time, the digitized information coming from the front-end electronics and send it to the Read-Out System. Data processing in the ROD boards is performed in Processing Unit Mezzanine Cards that use commercial DSPs to run the Optimal Filtering (OF) algorithms.
AGATA-Advanced GAmma Tracking Array
WOS: 000300864200005