0000000000161894

AUTHOR

Sebastian Meisner

showing 1 related works from this author

Parallel macro pipelining on the intel SCC many-core computer

2013

In this paper we present how Intel's Single-Chip-Cloud processor behaves for parallel macro pipeline applications. Subsets of the SCC's available cores can be arranged as a pipeline where each core processes one stage of the overall workload. Each of the independent cores processes a small part of a larger task and feeds the following core with new data after it finishes its work. Our case-study is a parallel rendering system which renders successive images and applies different filters on them. On normal graphics adapters this is usually done in multiple cycles, we do this in a single pipeline pass. We show that we can achieve a significant speedup by using multiple parallel pipelines on t…

Hardware_MEMORYSTRUCTURESSpeedupParallel renderingbusiness.industryComputer sciencePipeline (computing)020207 software engineering02 engineering and technologyParallel computingGraphics pipelineSingle-chip Cloud ComputerMemory bankParallel processing (DSP implementation)Embedded system0202 electrical engineering electronic engineering information engineeringMacrobusiness
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