0000000000266326
AUTHOR
A. Perez-pascual
Area-efficient FPGA-based FFT processor
A novel architecture for computing the fast Fourier transform on programmable devices is presented. Main results indicate that the use of one CORDIC operator to perform the multiplication by all the ‘twiddle factors’ sequentially leads to an area saving up to 35% with respect to other cores.
Design of an efficient digital down-converter for a SDR-based DVB-S receiver
This paper presents the design of an area-power efficient digital down-converter suitable for broadband communication systems. The DVB-S standard has been used as a design example. It has been shown that by selecting a bandpass sampling to generate only one spectral image, the case in which the relationship between the digital carrier frequency and the sampling frequency is 1/4, not only gives the smallest area but the lowest power consumption.
Efficient pipeline FFT processors for WLAN MIMO-OFDM systems
The most area-efficient pipeline FFT processors for WLAN MIMO-OFDM systems are presented. It is shown that although the R2/sup 3/SDF architecture is the most area-efficient approach for implementing pipeline FFT processors, RrMDC architectures are more efficient in MIMO-OFDM systems when more than three channels are used.