6533b7d5fe1ef96bd1264fd1
RESEARCH PRODUCT
Area-efficient FPGA-based FFT processor
A. Perez-pascualT. SansaloniJavier Vallssubject
Cooley–Tukey FFT algorithmSplit-radix FFT algorithmComputer sciencebusiness.industryFast Fourier transformPrime-factor FFT algorithmMultiplicationElectrical and Electronic EngineeringCORDICField-programmable gate arraybusinessTwiddle factorComputer hardwaredescription
A novel architecture for computing the fast Fourier transform on programmable devices is presented. Main results indicate that the use of one CORDIC operator to perform the multiplication by all the ‘twiddle factors’ sequentially leads to an area saving up to 35% with respect to other cores.
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2003-01-01 | Electronics Letters |