0000000000315442

AUTHOR

Mohit Upadhyay

showing 4 related works from this author

Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration

2018

Increase in the processing elements in a System-on- Chip (SoC) has led to an increasing complexity between the cores in the entire network. This communication bottleneck led to rise in the new paradigm called Network-on-Chip (NoC). These NoC are very much susceptible to various types of faults which can be transient, intermittent or permanent. This paper presents a fault-tolerant routing technique which can route the packets from a source to a destination in presence of permanent faults in the leaf routers of Mesh-of-Tree topology where cores are connected. This is achieved by using reconfiguration in the local ports of the leaf routers by inserting multiplexers as a layer between the leaf …

RouterComputer sciencebusiness.industryNetwork packetComputerSystemsOrganization_COMPUTER-COMMUNICATIONNETWORKS020208 electrical & electronic engineeringControl reconfigurationTopology (electrical circuits)Hardware_PERFORMANCEANDRELIABILITY02 engineering and technologyNetwork topologyMultiplexerBottleneck020204 information systemsHardware_INTEGRATEDCIRCUITS0202 electrical engineering electronic engineering information engineeringRouting (electronic design automation)businessComputer network2018 International Conference on High Performance Computing & Simulation (HPCS)
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A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design

2018

Due to the increase in the number of processing elements in System-on-Chips (SoCs), communication between the cores is becoming complex. A solution to this issue in SoCs gave rise to a new paradigm called Network-on-Chips (NoCs). In NoCs, communication between different cores is achieved using packet based switching techniques. In the deep sub-micron technology, NoCs are more susceptible to different kinds of faults which can be transient, intermittent and permanent. These faults can occur at any component of NoCs. This paper presents a novel Fault-Tolerant Routing (FTR) technique for Mesh-of-Tree (MoT) topology in the presence of router faults. The proposed technique is compared with routi…

RouterComputer sciencebusiness.industryNetwork packet020208 electrical & electronic engineeringTopology (electrical circuits)Fault toleranceHardware_PERFORMANCEANDRELIABILITY02 engineering and technologyNetwork topology020204 information systemsHardware_INTEGRATEDCIRCUITS0202 electrical engineering electronic engineering information engineeringNode (circuits)Transient (computer programming)Routing (electronic design automation)businessComputer network
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A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips

2019

Use of bus architecture based communication with increasing processing elements in System-on-Chip (SoC) leads to severe degradation of performance and speed of the system. This bottleneck is overcome with the introduction of Network-on-Chips (NoCs). NoCs assist in communication between cores on a single chip using router based packet switching technique. Due to miniaturization, NoCs like every Integrated circuit is prone to different kinds of faults which can be transient, intermittent or permanent. A fault in any one component of such a crucial network can degrade performance leaving other components non-usable. This paper presents a novel Fault-Tolerant routing Algorithm for Mesh-of-Tree …

010302 applied physicsRouterNetwork packetbusiness.industryComputer scienceFault toleranceTopology (electrical circuits)Hardware_PERFORMANCEANDRELIABILITY02 engineering and technologyFault (power engineering)01 natural sciencesBottleneckPacket switching020204 information systems0103 physical sciencesHardware_INTEGRATEDCIRCUITS0202 electrical engineering electronic engineering information engineeringRouting (electronic design automation)businessComputer network
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Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture

2019

This paper outlines a multi-application mapping for Mesh-of-Tree (MoT) topology based Network-on-Chip (NoC) design using reconfigurable architecture. A two phase Particle Swarm Optimization (PSO) has been proposed for reconfigurable architecture to minimize the communication cost. In first phase global mapping is done by combining multiple applications and in second phase, reconfiguration is achieved by switching the cores to near by routers using multiplexers. Experimentations have been carried out for several application benchmarks and synthetic applications generated using TGFF tool. The results show significant improvement in terms of communication cost after reconfiguration.

020203 distributed computingComputer scienceControl reconfigurationParticle swarm optimizationTopology (electrical circuits)02 engineering and technologyNetwork topologyMultiplexingMultiplexer020202 computer hardware & architectureNetwork on a chipComputer architecture0202 electrical engineering electronic engineering information engineeringArchitecture2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)
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