6533b856fe1ef96bd12b3001

RESEARCH PRODUCT

Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture

Soumya JP. Veda BhanuMohit UpadhyayMonil ShahLinga Reddy Cenkeramaddi

subject

020203 distributed computingComputer scienceControl reconfigurationParticle swarm optimizationTopology (electrical circuits)02 engineering and technologyNetwork topologyMultiplexingMultiplexer020202 computer hardware & architectureNetwork on a chipComputer architecture0202 electrical engineering electronic engineering information engineeringArchitecture

description

This paper outlines a multi-application mapping for Mesh-of-Tree (MoT) topology based Network-on-Chip (NoC) design using reconfigurable architecture. A two phase Particle Swarm Optimization (PSO) has been proposed for reconfigurable architecture to minimize the communication cost. In first phase global mapping is done by combining multiple applications and in second phase, reconfiguration is achieved by switching the cores to near by routers using multiplexers. Experimentations have been carried out for several application benchmarks and synthetic applications generated using TGFF tool. The results show significant improvement in terms of communication cost after reconfiguration.

yearjournalcountryeditionlanguage
2019-01-012019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)
https://doi.org/10.1109/vlsid.2019.00119