Fabrication and characterization of small tunnel junctions through a thin dielectric membrane

1998

We show that a small tapered hole through a thin silicon nitride membrane provides a mask for tunnel junction structures. Our experiments imply, unlike in the conventional planar electron beam lithography, that tunnel junctions are well voltage biased in this structure with vanishingly small on-chip impedance. Our technique allows fabrication of double junctions, and even multijunction linear arrays, with small metallic islands in between.