0000000000559254

AUTHOR

Jesús Camacho

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Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems

2011

[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of usi…

RouterComputer scienceRouting tableDistributed computing02 engineering and technologyMPSoCNetwork topology01 natural sciencesNetworks-on-chip0103 physical sciences0202 electrical engineering electronic engineering information engineeringElectrical and Electronic EngineeringRouting010302 applied physicsStatic routingbusiness.industryComputer Graphics and Computer-Aided Design020202 computer hardware & architectureFault-toleranceARQUITECTURA Y TECNOLOGIA DE COMPUTADORESNetwork on a chip13. Climate actionLogic designEmbedded systemScalabilityMultipath routingbusinessSoftwareIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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